Level shifter and display device

ABSTRACT

Embodiments of the present disclosure relate to a level shifter and a display device capable of differently controlling a signal waveform between a first clock signal and a second clock signal used to output a first gate signal and a second gate signal. Accordingly, it is possible to reduce the variation in output characteristics between the first gate signal and the second gate signal, thereby improving image quality.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit and priority from Republic of KoreaPatent Application No. 10-2020-0183579, filed in the Republic of Koreaon Dec. 24, 2020, which is hereby incorporated by reference in itsentirety.

BACKGROUND Technical Field

The present disclosure relates to a level shifter and a display device.

Description of the Related Art

As the information society develops, demand for a display device fordisplaying an image is increasing in various forms, and in recent years,various display devices such as a liquid crystal display device and anorganic light emitting display device are used.

A conventional display device may charge a capacitor disposed in each ofa plurality of sub-pixels arranged on a display panel and use thecapacitors to drive the display. However, in the case of a conventionaldisplay device, a phenomenon in which charging is insufficient in eachsub-pixel may occur, resulting in a problem of deteriorating imagequality.

In a conventional display device, if the size of the non-display area ofthe display panel can be reduced, the degree of freedom in design of thedisplay device can be increased, and design quality can also beimproved. However, it is not easy to reduce the non-display area of thedisplay panel because various wires and circuits must be arranged in thenon-display area of the display panel.

In addition, in the case of a conventional display device, not only theimage quality is degraded due to insufficient charging time, but alsothe gate driving may malfunction due to the characteristic variation ofthe gate signals, resulting in deterioration of the image quality.

SUMMARY

Embodiments of the present disclosure provide a level shifter and adisplay device that can reduce a characteristic variation between gatesignals and thereby improve image quality.

Embodiments of the present disclosure provide a level shifter and adisplay device capable of variously controlling a rising characteristicand/or a falling characteristic of clock signals.

Embodiments of the present disclosure provide a level shifter and adisplay device capable of reducing the size of an arrangement area ofthe gate driving circuit and reducing characteristic variation betweengate signals even if the gate driving circuit is disposed on the displaypanel in a panel built-in type.

According to aspects of the present disclosure, there are a levelshifter including: a first output terminal outputting a first clocksignal; a second output terminal outputting a second clock signal havinga different rising length or a different falling length than the firstclock signal; a high input terminal to which a high level voltage isinput; a low input terminal to which a low level voltage is input; anintermediate input terminal to which an intermediate level voltage isinput; a first clock output circuit including a first rising switch forcontrolling an electrical connection between the high input terminal andthe first output terminal, a first falling switch for controlling anelectrical connection between the low input terminal and the firstoutput terminal, and a first gate pulse modulation switch forcontrolling an electrical connection between the intermediate inputterminal and the first output terminal; and a second clock outputcircuit including a second rising switch for controlling an electricalconnection between the high input terminal and the second outputterminal, a second falling switch controlling an electrical connectionbetween the low input terminal and the second output terminal, and asecond gate pulse modulation switch for controlling an electricalconnection between the intermediate input terminal and the second outputterminal.

A falling length of the first clock signal may be longer than a fallinglength of the second clock signal.

An on-resistance of the first gate pulse modulation switch when thefirst clock signal falls may be greater than an on-resistance of thesecond gate pulse modulation switch when the second clock signal falls.

In another embodiment, an on-resistance of the first falling switch whenthe first clock signal falls may be greater than an on-resistance of thesecond falling switch when the second clock signal falls.

A rising length of the second clock signal may be longer than a risinglength of the first clock signal.

An on-resistance of the second gate pulse modulation switch when thesecond clock signal rises may be greater than an on-resistance of thefirst gate pulse modulation switch when the first clock signal rises.

An on-resistance of the second rising switch when the second clocksignal rises may be greater than an on-resistance of the first risingswitch when the first clock signal rises.

An on-resistance of the first gate pulse modulation switch when thefirst clock signal falls may be greater than the on-resistance of thefirst gate pulse modulation switch when the first clock signal rises.

An on-resistance of the second gate pulse modulation switch when thesecond clock signal rises may be greater than the on-resistance of thesecond gate pulse modulation switch when the second clock signal falls.

The level shifter may further include a clock control circuit configuredto control the first clock output circuit and the second clock outputcircuit based on a generation clock signal and a modulation clocksignal.

The clock control circuit may output control signals for controllingon-off of each of the first rising switch, the first falling switch, andthe first gate pulse modulation switch based on a first pulse of thegeneration clock signal and a first pulse of the modulation clocksignal.

The clock control circuit may output control signals for controllingon-off of each of the second rising switch, the second falling switch,and the second gate pulse modulation switch based on a second pulse ofthe generation clock signal and a second pulse of the modulation clocksignal.

The first gate pulse modulation switch may include two or more firstsub-switches connected in parallel between the intermediate inputterminal and the first output terminal and independently controlledon-off.

An on-resistance of the first gate pulse modulation switch may be ininverse proportion to the number of turned-on first sub-switches amongthe two or more first sub-switches.

The second gate pulse modulation switch may include two or more secondsub-switches connected in parallel between the intermediate inputterminal and the second output terminal.

An on-resistance of the second gate pulse modulation switch may be ininverse proportion to the number of turned-on second sub-switches amongthe two or more second sub-switches.

The level shifter may further include a clock control circuit configuredto control a first gate voltage and a second gate voltage. The firstgate voltage is a control signal for controlling on-off of the firstgate pulse modulation switch. The second gate voltage is a controlsignal for controlling on-off of the second gate pulse modulationswitch.

An on-resistance of the first gate pulse modulation switch may bechanged according to the first gate voltage, and an on-resistance of thesecond gate pulse modulation switch may be changed according to thesecond gate voltage.

According to aspects of the present disclosure, there are a displaydevice including: a substrate; a plurality of gate lines disposed on thesubstrate; and a gate driving circuit disposed on or connected to thesubstrate and configured to output a first gate signal and a second gatesignal to a first gate line and a second gate line among the pluralityof gate lines based on a first clock signal and a second clock signal.

The gate driving circuit includes: a first gate output buffer circuitfor outputting the first gate signal based on the first clock signal; asecond gate output buffer circuit for outputting the second gate signalbased on the second clock signal; and a gate output control circuit forcontrolling the first gate output buffer circuit and the second gateoutput buffer circuit.

The first gate output buffer circuit includes: a first pull-uptransistor connected between a first clock input terminal to which thefirst clock signal is input and a first gate output terminal to whichthe first gate signal is output; and a first pull-down transistorconnected between the first gate output terminal and a base inputterminal to which a base voltage is input.

The second gate output buffer circuit includes: a second pull-uptransistor connected between a second clock input terminal to which thesecond clock signal is input and a second gate output terminal to whichthe second gate signal is output; and a second pull-down transistorconnected between the second gate output terminal and a base inputterminal to which a base voltage is input.

A gate node of the first pull-up transistor and a gate node of thesecond pull-up transistor may be electrically connected. A gate node ofthe first pull-down transistor and a gate node of the second pull-downtransistor may be electrically connected.

A falling length of the first clock signal is different from a fallinglength of the second clock signal, or a rising length of the secondclock signal is different from a rising length of the first clocksignal.

According to embodiments of the present disclosure, it is possible toprovide the level shifter and the display device that can reduce acharacteristic variation between gate signals and thereby improve imagequality.

According to embodiments of the present disclosure, it is possible toprovide the level shifter and the display device capable of variouslycontrolling a rising characteristic and/or a falling characteristic ofclock signals.

According to embodiments of the present disclosure, it is possible toprovide the level shifter and the display device capable of reducing thesize of an arrangement area of the gate driving circuit and reducingcharacteristic variation between gate signals even if the gate drivingcircuit is disposed on the display panel in a panel built-in type.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and advantages of the presentdisclosure will be more apparent from the following detailed descriptiontaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a system configuration diagram of a display device accordingto embodiments of the present disclosure;

FIGS. 2A and 2B are equivalent circuits of sub-pixel of the displaydevice according to embodiments of the present disclosure;

FIG. 3 is an exemplary diagram illustrating a system implementation ofthe display device according to embodiments of the present disclosure;

FIG. 4 illustrates a gate signal output system of the display deviceaccording to embodiments of the present disclosure;

FIG. 5 is a gate driving circuit having a structure in which two gateoutput buffer circuits share one Q node in the display device accordingto embodiments of the present disclosure;

FIG. 6 is a diagram illustrating a characteristic deviation between gatesignals output from the gate driving circuit of FIG. 5 according toembodiments of the present disclosure;

FIGS. 7A, 7B, and 7C are diagrams for explaining a characteristicdeviation compensation function between gate signals output from thegate driving circuit of FIG. 5 according to embodiments of the presentdisclosure;

FIG. 8 is a level shifter according to embodiments of the presentdisclosure;

FIG. 9 is a driving timing diagram for the level shifter according toembodiments of the present disclosure;

FIG. 10 is a driving timing diagram for explaining two options forfalling control of a first clock signal of the level shifter accordingto embodiments of the present disclosure;

FIG. 11A is a driving timing diagram illustrating a first option forfalling control of the first clock signal of the level shifter accordingto embodiments of the present disclosure;

FIG. 11B is a driving timing diagram illustrating a second option forfalling control of the first clock signal of the level shifter accordingto embodiments of the present disclosure;

FIG. 12 is a driving timing diagram for explaining two options forrising control of a second clock signal of the level shifter accordingto embodiments of the present disclosure;

FIG. 13A is a driving timing diagram illustrating a first option forrising control of the second clock signal of the level shifter accordingto embodiments of the present disclosure;

FIG. 13B is a driving timing diagram illustrating a second option forrising control of the second clock signal of the level shifter accordingto embodiments of the present disclosure;

FIG. 14A is a driving timing diagram illustrating the first option forfalling control of the first clock signal based on a modulation clocksignal output from the controller of the display device according toembodiments of the present disclosure;

FIG. 14B is a driving timing diagram illustrating the second option forfalling control of the first clock signal based on the modulation clocksignal output from the controller of the display device according toembodiments of the present disclosure;

FIG. 15A is a diagram illustrating a switch split technique foradjusting on-resistance of the first gate pulse modulation switch of thelevel shifter according to embodiments of the present disclosure;

FIG. 15B is a diagram illustrating a switch split technique foradjusting on-resistance of the second gate pulse modulation switch ofthe level shifter according to embodiments of the present disclosure;

FIG. 16A is a diagram for explaining a gate-source voltage Vgs controltechnique for adjusting an on-resistance of the first gate pulsemodulation switch of the level shifter according to embodiments of thepresent disclosure;

FIG. 16B is a diagram for explaining a gate-source voltage Vgs controltechnique for adjusting an on-resistance of the second gate pulsemodulation switch of the level shifter according to embodiments of thepresent disclosure;

FIG. 17 illustrates a gate signal output system of the display deviceaccording to embodiments of the present disclosure;

FIG. 18 is a gate driving circuit having a structure in which four gateoutput buffer circuits share one Q node in the display device accordingto embodiments of the present disclosure;

FIG. 19 is a diagram illustrating a characteristic deviation betweengate signals output from the gate driving circuit of FIG. 18 accordingto embodiments of the present disclosure;

FIG. 20 is a diagram for explaining a characteristic deviationcompensation function between gate signals output from the gate drivingcircuit of FIG. 18 according to embodiments of the present disclosure;

FIG. 21 is the level shifter according to embodiments of the presentdisclosure;

FIG. 22 is a graph for explaining an effect of the characteristicdeviation compensation function between gate signals under the Q nodesharing structure as shown in FIG. 5 in the display device according toembodiments of the present disclosure; and

FIG. 23 is a diagram for explaining an effect of a characteristicdeviation compensation function between gate signals under the Q nodesharing structure as shown in FIG. 18 in the display device according toembodiments of the present disclosure.

DETAILED DESCRIPTION

In the following description of examples or embodiments of the presentinvention, reference will be made to the accompanying drawings in whichit is shown by way of illustration specific examples or embodiments thatcan be implemented, and in which the same reference numerals and signscan be used to designate the same or like components even when they areshown in different accompanying drawings from one another. Further, inthe following description of examples or embodiments of the presentinvention, detailed descriptions of well-known functions and componentsincorporated herein will be omitted when it is determined that thedescription may make the subject matter in some embodiments of thepresent invention rather unclear. The terms such as “including”,“having”, “containing”, “constituting” “make up of”, and “formed of”used herein are generally intended to allow other components to be addedunless the terms are used with the term “only”. As used herein, singularforms are intended to include plural forms unless the context clearlyindicates otherwise.

Terms, such as “first”, “second”, “A”, “B”, “(A)”, or “(B)” may be usedherein to describe elements of the present invention. Each of theseterms is not used to define essence, order, sequence, or number ofelements etc., but is used merely to distinguish the correspondingelement from other elements.

When it is mentioned that a first element “is connected or coupled to”,“contacts or overlaps” etc. a second element, it should be interpretedthat, not only can the first element “be directly connected or coupledto” or “directly contact or overlap” the second element, but a thirdelement can also be “interposed” between the first and second elements,or the first and second elements can “be connected or coupled to”,“contact or overlap”, etc. each other via a fourth element. Here, thesecond element may be included in at least one of two or more elementsthat “are connected or coupled to”, “contact or overlap”, etc. eachother.

When time relative terms, such as “after,” “subsequent to,” “next,”“before,” and the like, are used to describe processes or operations ofelements or configurations, or flows or steps in operating, processing,manufacturing methods, these terms may be used to describenon-consecutive or non-sequential processes or operations unless theterm “directly” or “immediately” is used together.

In addition, when any dimensions, relative sizes etc. are mentioned, itshould be considered that numerical values for an elements or features,or corresponding information (e.g., level, range, etc.) include atolerance or error range that may be caused by various factors (e.g.,process factors, internal or external impact, noise, etc.) even when arelevant description is not specified. Further, the term “may” fullyencompasses all the meanings of the term “can”.

FIG. 1 is a system configuration diagram of a display device 100according to embodiments of the present disclosure.

Referring to FIG. 1, the display device 100 according to embodiments ofthe present disclosure may include a display panel 110 and a drivingcircuit for driving the display panel 110.

The driving circuit may include a data driving circuit 120 and a gatedriving circuit 130, and may further include a controller 140 forcontrolling the data driving circuit 120 and the gate driving circuit130.

The display panel 110 may include a substrate SUB and signal lines suchas a plurality of data lines DL and a plurality of gate lines GLdisposed on the substrate SUB. The display panel 110 may include aplurality of sub-pixels SP connected to a plurality of data lines DL anda plurality of gate lines GL.

The display panel 110 may include a display area DA in which an image isdisplayed and a non-display area NDA in which an image is not displayed.The plurality of sub-pixels SP for displaying an image may be disposedin the display area DA of the display panel 110. In the non-display areaNDA of the display panel 110, at least one of the driving circuits 120,130, and 140 may be electrically connected or at least one of thedriving circuits 120, 130, and 140 may be mounted. A pad portion towhich an integrated circuit or a printed circuit is connected may bedisposed in the non-display area NDA of the display panel 110.

The data driving circuit 120 is a circuit for driving the plurality ofdata lines DL, and may supply data signals to the plurality of datalines DL. The gate driving circuit 130 is a circuit for driving theplurality of gate lines GL, and may supply gate signals to the pluralityof gate lines GL. The controller 140 may supply a data control signalDCS to the data driving circuit 120 to control the operation timing ofthe data driving circuit 120. The controller 140 may supply a gatecontrol signal GCS for controlling the operation timing of the gatedriving circuit 130 to the gate driving circuit 130.

The controller 140 may start a scan according to timing implemented ineach frame, and may control data drive at an appropriate time accordingto the scan. The controller 140 may convert input image data input fromthe outside according to a data signal format used by the data drivingcircuit 120 and supply the converted image data Data to the data drivingcircuit 120.

The controller 140 may receive various timing signals from the outside(e.g., host system 150) together with the input image data. For example,various timing signals may include a vertical synchronization signal(VSYNC), a horizontal synchronization signal (HSYNC), an input dataenable signal DE, and a clock signal.

In order to control the data driving circuit 120 and the gate drivingcircuit 130, the controller 140 may receive the timing signals (e.g.,VSYNC, HSYNC, DE, clock signal, etc.) to generate the various controlsignals (e.g., DCS, GCS, etc.), and may output the generated variouscontrol signals (e.g., DCS, GCS, etc.) to the data driving circuit 120and the gate driving circuit 130.

For example, the controller 140 may output various gate control signalsGCS including a gate start pulse (GSP), a gate shift clock (GSC), and agate output enable signal (GOE) to control the gate driving circuit 130.

In addition, the controller 140 may output various data control signalsDCS including a source start pulse (SSP), a source sampling clock (SSC),and a source output enable signal (SOE) to control the data drivingcircuit 120.

The controller 140 may be implemented as a separate component from thedata driving circuit 120, or may be integrated with the data drivingcircuit 120 and implemented as an integrated circuit.

The data driving circuit 120 may drive the plurality of data lines DL byreceiving image data Data from the controller 140 and supplying datavoltages to the plurality of data lines DL. Here, the data drivingcircuit 120 is also referred to as a source driving circuit.

The data driving circuit 120 may include one or more source driverintegrated circuits (SDICs).

Each source driver integrated circuit (SDIC) may include a shiftregister, a latch circuit, a digital to analog converter (DAC), anoutput buffer, and the like. Each source driver integrated circuit(SDIC) may further include an analog to digital converter (ADC) in somecases.

For example, each source driver integrated circuit (SDIC) may beconnected to the display panel 110 in a TAB (tape automated bonding)type, connected to a bonding pad of the display panel 110 in a COG(chip-on-glass) type or a COP (chip-on-panel) type, or implemented in aCOF (chip-on-film) type to be connected to the display panel 110.

The gate driving circuit 130 may output a gate signal of a turn-on levelvoltage or a gate signal of a turn-off level voltage under the controlof the controller 140. The gate driving circuit 130 may sequentiallydrive the plurality of gate lines GL by sequentially supplying a gatesignal having a turn-on level voltage to the plurality of gate lines GL.

The gate driving circuit 130 may be connected to the display panel 110in a TAB type, connected to a bonding pad of the display panel 110 in aCOG type or a COP type, or implemented as a COF type to be connected tothe display panel 110. Alternatively, the gate driving circuit 130 maybe formed in the non-display area NDA of the display panel 110 in a GIP(gate-in-panel) type. The gate driving circuit 130 may be disposed on orconnected to the substrate SUB. As described above, in the case of theGIP type, the gate driving circuit 130 may be disposed in thenon-display area NDA of the substrate SUB. The gate driving circuit 130may be connected to the substrate SUB in the case of a COG type, a COFtype, or the like.

Meanwhile, at least one of the data driving circuit 120 and the gatedriving circuit 130 may be disposed in the display area DA. For example,at least one of the data driving circuit 120 and the gate drivingcircuit 130 may be disposed so as not to overlap the sub-pixels SP.Alternatively, at least one of the data driving circuit 120 and the gatedriving circuit 130 may be disposed to partially or entirely overlap thesub-pixels SP.

When any one gate line GL is driven by the gate driving circuit 130, thedata driving circuit 120 may convert the image data received from thecontroller 140 into an analog data voltage and supply the converted datavoltage to the plurality of data lines DL.

The data driving circuit 120 may be connected to one side (e.g., anupper side or a lower side) of the display panel 110. Depending on thedriving method, the panel design method, etc., the data driving circuit120 may be connected to both sides (e.g., upper and lower sides) of thedisplay panel 110 or to two or more of the four sides of the displaypanel 110.

The gate driving circuit 130 may be connected to one side (e.g., leftside or right side) of the display panel 110. Depending on the drivingmethod, the panel design method, etc., the gate driving circuit 130 maybe connected to both sides (e.g., left side and right side) of thedisplay panel 110 or to at least two of the four sides of the displaypanel 110.

The controller 140 may be a timing controller used in a typical displaytechnology. Alternatively, the controller 140 may be a control devicecapable of further performing other control functions in addition to thefunctions of the timing controller. Alternatively, the controller 140may be a control device different from the timing controller, or may bea circuit within the control device. For example, the controller 140 maybe implemented with various circuits or electronic components, such asan integrated circuit (IC), a field programmable gate array (FPGA), anapplication specific integrated circuit (ASIC), or a processor.

The controller 140 may be mounted on a printed circuit board, a flexibleprinted circuit, etc., and may be electrically connected to the datadriving circuit 120 and the gate driving circuit 130 through the printedcircuit board, the flexible printed circuit, etc.

The controller 140 may transmit and receive signals to and from the datadriving circuit 120 according to one or more predetermined interfaces.Here, for example, the interface may include a low voltage differentialsignaling (LVDS) interface, an EPI interface, and a serial peripheralinterface (SPI).

The controller 140 may include a storage medium such as one or moreregisters.

The display device 100 according to embodiments of the presentdisclosure may be a display including a backlight unit such as a liquidcrystal display, or a self-luminous display in which the display panel110 emits light by itself. For example, the self-luminous display may beone of an organic light emitting diode (OLED) display, a quantum dotdisplay, an inorganic-based light emitting diode display, and the like.

When the display device 100 according to embodiments of the presentdisclosure is an OLED display, each sub-pixel SP may include an organiclight emitting diode (OLED) emitting light as a light emitting device.When the display device 100 according to the present exemplaryembodiment is a quantum dot display, each sub-pixel SP may include alight emitting device made of quantum dots, which are semiconductorcrystals that emit light by themselves. When the display device 100according to the present embodiments is an LED display, each sub-pixelSP emits light by itself and may include a micro LED (micro lightemitting diode) made of an inorganic material as a light emittingdevice.

FIGS. 2A and 2B are equivalent circuits of sub-pixel SP of the displaydevice 100 according to embodiments of the present disclosure.

Referring to FIG. 2A, each of the plurality of sub-pixels SP disposed onthe display panel 110 of the display device 100 according to embodimentsof the present disclosure may include a light emitting device ED, adriving transistor DRT, a scan transistor SCT, and a storage capacitorCst.

Referring to FIG. 2A, the light emitting device ED may include a pixelelectrode PE and a common electrode CE, and may include a light emittinglayer EL positioned between the pixel electrode PE and the commonelectrode CE.

The pixel electrode PE of the light emitting device ED may be anelectrode disposed in each sub-pixel SP, and the common electrode CE maybe an electrode commonly disposed in all sub-pixels SP. Here, the pixelelectrode PE may be an anode electrode and the common electrode CE maybe a cathode electrode. Conversely, the pixel electrode PE may be acathode electrode and the common electrode CE may be an anode electrode.

For example, the light emitting device ED may be an organic lightemitting diode (OLED), a light emitting diode (LED), or a quantum dotlight emitting device.

The driving transistor DRT may be a transistor for driving the lightemitting device ED, and may include a first node N1, a second node N2, athird node N3, and the like.

The first node N1 of the driving transistor DRT may be a gate node ofthe driving transistor DRT, and may be electrically connected to asource node or a drain node of the scan transistor SCT. The second nodeN2 of the driving transistor DRT may be a source node or a drain node ofthe driving transistor DRT, and may be electrically connected to thepixel electrode PE of the light emitting device ED. The third node N3 ofthe driving transistor DRT may be electrically connected to the drivingvoltage line DVL supplying the driving voltage EVDD.

The scan transistor SCT is controlled by a scan signal SCAN, which is atype of a gate signal, and may be connected between the first node N1 ofthe driving transistor DRT and the data line DL. In other words, thescan transistor SCT may be turned on or off according to the scan signalSCAN supplied from the scan signal line SCL, which is one type of thegate line GL. Accordingly, the scan transistor SCT may control theconnection between the data line DL and the first node N1 of the drivingtransistor DRT.

The scan transistor SCT may be turned on by the scan signal SCAN havinga turn-on level voltage to transfer the data voltage Vdata supplied fromthe data line DL to the first node N1 of the driving transistor DRT.

Here, when the scan transistor SCT is an n-type transistor, the turn-onlevel voltage of the scan signal SCAN may be a high level voltage. Whenthe scan transistor SCT is a p-type transistor, the turn-on levelvoltage of the scan signal SCAN may be a low level voltage.

The storage capacitor Cst may be connected between the first node N1 andthe second node N2 of the driving transistor DRT. The storage capacitorCst may be charged with an amount of charge corresponding to the voltagedifference between the terminals, and may serve to maintain the voltagedifference between the terminals for a predetermined frame time.Accordingly, during a predetermined frame time, the correspondingsub-pixel SP may emit light.

Referring to FIG. 2B, each of the plurality of sub-pixels SP disposed onthe display panel 110 of the display device 100 according to embodimentsof the present disclosure may further include a sensing transistor SENT.

The sensing transistor SENT may be controlled by a sense signal SENSE,which is a type of a gate signal, and may be connected between thesecond node N2 of the driving transistor DRT and the reference voltageline RVL. The sensing transistor SENT may be turned on or turned offaccording to the sense signal SENSE supplied from the sense signal lineSENL, which is a type of the gate line GL, to control the connectionbetween the reference voltage line RVL and the second node N2 of thedriving transistor DRT.

The sensing transistor SENT may be turned on by the sense signal SENSEhaving a turn-on level voltage, and may transfer the reference voltageVref supplied from the reference voltage line RVL to the second node N2of the driving transistor DRT.

In addition, the sensing transistor SENT may be turned on by the sensesignal SENSE having a turn-on level voltage to transfer the voltage ofthe second node N2 of the driving transistor DRT to the referencevoltage line RVL. At this time, the reference voltage line RVL may be ina state to which the reference voltage Vref is not applied.

Here, when the sensing transistor SENT is an n-type transistor, theturn-on level voltage of the sense signal SENSE may be a high levelvoltage. When the sensing transistor SENT is a p-type transistor, theturn-on level voltage of the sense signal SENSE may be a low levelvoltage.

A function in which the sensing transistor SENT transfers the voltage ofthe second node N2 of the driving transistor DRT to the referencevoltage line RVL may be used during driving to sense the characteristicvalue of the sub-pixel SP. In this case, the voltage transferred to thereference voltage line RVL may be a voltage for calculating thecharacteristic value of the sub-pixel SP or a voltage in which thecharacteristic value of the sub-pixel SP is reflected.

In the present disclosure, the characteristic value of the sub-pixel SPmay be a characteristic value of the driving transistor DRT or the lightemitting device ED. The characteristic value of the driving transistorDRT may include a threshold voltage and mobility of the drivingtransistor DRT. The characteristic value of the light emitting device EDmay include a threshold voltage of the light emitting device ED.

Each of the driving transistor DRT, the scan transistor SCT, and thesensing transistor SENT may be an n-type transistor or a p-typetransistor. In the present disclosure, for convenience of description,it is assumed that each of the driving transistor DRT, the scantransistor SCT, and the sensing transistor SENT is an n-type.

The storage capacitor Cst may not be a parasitic capacitor (e.g.,gate-source parasitic capacitance Cgs, gate-drain parasitic capacitanceCgd) that is an internal capacitor existing between the gate node andthe source node (or drain node) of the driving transistor DRT, but maybe an external capacitor intentionally designed outside the drivingtransistor DRT.

The scan signal line SCL and the sense signal line SENL may be differentgate lines GL. In this case, the scan signal SCAN and the sense signalSENSE may be separate gate signals, the on-off timing of the scantransistor SCT and the on-off timing of the sensing transistor SENT inone sub-pixel SP may be independent. That is, the on-off timing of thescan transistor SCT and the on-off timing of the sensing transistor SENTin one sub-pixel SP may be the same or different.

Alternatively, the scan signal line SCL and the sense signal line SENLmay be the same gate line GL. That is, the gate node of the scantransistor SCT and the gate node of the sensing transistor SENT in onesub-pixel SP may be connected to one gate line GL. In this case, thescan signal SCAN and the sense signal SENSE may be the same gate signal,the on-off timing of the scan transistor SCT and the on-off timing ofthe sensing transistor SENT in one sub-pixel SP may be the same.

The structure of the sub-pixel SP shown in FIGS. 2A and 2B is merely anexample, and the sub-pixel SP further includes one or more transistorsor includes one or more capacitors and may be variously modified.

In addition, the sub-pixel structure illustrated in FIGS. 2A and 2B hasbeen described on the assumption that the display device 100 is aself-luminous display device. When the display device 100 is a liquidcrystal display, each sub-pixel SP may include a transistor and a pixelelectrode.

FIG. 3 is an exemplary diagram illustrating a system implementation ofthe display device 100 according to embodiments of the presentdisclosure.

Referring to FIG. 3, the display panel 110 may include the display areaDA in which an image is displayed and the non-display area NDA in whichan image is not displayed.

Referring to FIG. 3, when the data driving circuit 120 includes at leastone source driver integrated circuit SDIC and is implemented as a COFtype, each source driver integrated circuit SDIC may be mounted on thecircuit film SF connected to the non-display area NDA of the displaypanel 110.

Referring to FIG. 3, the gate driving circuit 130 may be implemented asa GIP type. In this case, the gate driving circuit 130 may be formed inthe non-display area NDA of the display panel 110. Alternatively, thegate driving circuit 130 may be implemented as a COF type.

The display device 100 may include at least one source printed circuitboard SPCB for circuit connection between one or more source driverintegrated circuits SDIC and other devices, and a control printedcircuit board CPCB for mounting control elements (e.g., controller 140)and various electrical devices.

The circuit film SF on which the source driver integrated circuit SDICis mounted may be connected to at least one source printed circuit boardSPCB. More specifically, the source driver integrated circuit SDIC maybe mounted on the circuit film SF. A portion of the circuit film SF maybe electrically connected to the display panel 110, and another portionof the circuit film SF may be electrically connected to the sourceprinted circuit board SPCB.

The controller 140 and a power management integrated circuit 310 may bemounted on the control printed circuit board CPCB. The controller 140may perform overall control functions related to driving of the displaypanel 110, and may control operations of the data driving circuit 120and the gate driving circuit 130. The power management integratedcircuit 310 may supply various voltages or currents to the data drivingcircuit 120 and the gate driving circuit 130, or may control variousvoltages or currents to be supplied to the data driving circuit 120 andthe gate driving circuit 130.

At least one source printed circuit board SPCB and the control printedcircuit board CPCB may be connected through at least one connectioncable CBL. For example, the connection cable CBL may include a flexibleprinted circuit (FPC), a flexible flat cable (FFC), and the like.

At least one source printed circuit board SPCB and the control printedcircuit board CPCB may be implemented by being integrated into oneprinted circuit board.

The display device 100 according to embodiments of the presentdisclosure may further include a level shifter 300 for adjusting avoltage level. For example, the level shifter 300 may be disposed on thecontrol printed circuit board CPCB or the source printed circuit boardSPCB.

In particular, in the display device 100 according to embodiments of thepresent disclosure, the level shifter 300 may supply signals necessaryfor gate driving to the gate driving circuit 130. For example, the levelshifter 300 may supply a plurality of clock signals to the gate drivingcircuit 130. Accordingly, the gate driving circuit 130 may output theplurality of gate signals to the plurality of gate lines GL based on theplurality of clock signals input from the level shifter 300. Theplurality of gate lines GL may transmit the plurality of gate signals tothe sub-pixels SP disposed in the display area DA of the substrate SUB.

FIG. 4 illustrates a gate signal output system of the display device 100according to embodiments of the present disclosure.

Referring to FIG. 4, the level shifter 300 may output a first clocksignal CLK1 and a second clock signal CLK2 to the gate driving circuit130. The gate driving circuit 130 may generate and output the first gatesignal Vgout1 and the second gate signal Vgout2 based on the first clocksignal CLK1 and the second clock signal CLK2.

The first gate signal Vgout1 and the second gate signal Vgout2 may berespectively supplied to the first gate line GL1 and the second gateline GL2 disposed on the display panel 110. For example, each of thefirst gate signal Vgout1 and the second gate signal Vgout2 may be thescan signal SCAN applied to the gate node of the scan transistor SCT ofFIG. 2A or 2B. As another example, each of the first gate signal Vgout1and the second gate signal Vgout2 may be the sense signal SENSE appliedto the gate node of the sensing transistor SENT of FIG. 2B.

For example, when the gate driving circuit 130 performs gate driving in8 phases, the level shifter 300 may generate and output eight clocksignals CLK1 to CLK8, and the gate driving circuit 130 may perform gatedriving using eight clock signals CLK1 to CLK8.

FIG. 5 is a gate driving circuit having a structure in which two gateoutput buffer circuits GBUF1 and GBUF2 share one Q node in the displaydevice 100 according to embodiments of the present disclosure.

Referring to FIG. 5, the gate driving circuit 130 may receive the firstclock signal CLK1 and the second clock signal CLK2, and may output thefirst gate signal Vgout1 and the second gate signal Vgout2 to the firstgate line GL1 and the second gate line GL2 among the plurality of gatelines GL based on the first clock signal CLK1 and the second clocksignal CLK2.

The first gate line GL1 and the second gate line GL2 to which the firstgate signal Vgout1 and the second gate signal Vgout2 are applied may bedisposed adjacent to each other.

Alternatively, the first gate line GL1 and the second gate line GL2 towhich the first gate signal Vgout1 and the second gate signal Vgout2 areapplied may be disposed apart from each other. In this case, anothergate line GL may be disposed between the first gate line GL1 and thesecond gate line GL2.

The gate drive circuit 130 may include a first gate output buffercircuit GBUF1, a second gate output buffer circuit GBUF2, and a gateoutput control circuit 500. The first gate output buffer circuit GBUF1may output the first gate signal Vgout1 based on the first clock signalCLK1. The second gate output buffer circuit GBUF2 may output the secondgate signal Vgout2 based on the second clock signal CLK2. The gateoutput control circuit 500 may control the first gate output buffercircuit GBUF1 and the second gate output buffer circuit GBUF2.

The first gate output buffer circuit GBUF1 may include a first pull-uptransistor Tu1 and a first pull-down transistor Td1. The first pull-uptransistor Tu1 may be connected between a first clock input terminal Nc1to which the first clock signal CLK1 is input and a first gate outputterminal Ng1 to which the first gate signal Vgout1 is output. The firstpull-down transistor Td1 may be connected between the first gate outputterminal Ng1 and the base input terminal Ns to which a base voltage VSS1is input.

The second gate output buffer circuit GBUF2 may include a second pull-uptransistor Tu2 and a second pull-down transistor Td2. The second pull-uptransistor Tu2 may be connected between a second clock input terminalNc2 to which the second clock signal CLK2 is input and a second gateoutput terminal Ng2 to which the second gate signal Vgout2 is output.The second pull-down transistor Td2 may be connected between the secondgate output terminal Ng2 and the base input terminal Ns.

The gate output control circuit 500 may receive the start signal VST,the reset signal RST, and the like, and control the operations of thefirst gate output buffer circuit GBUF1 and the second gate output buffercircuit GBUF2. To this end, the gate output control circuit 500 maycontrol the voltage of the Q node and the voltage of the QB node.

Referring to FIG. 5, the gate node of the first pull-up transistor Tu1and the gate node of the second pull-up transistor Tu2 may beelectrically connected. That is, the gate node of the first pull-uptransistor Tu1 and the gate node of the second pull-up transistor Tu2may be commonly connected to the Q node.

Therefore, by the voltage of the Q node controlled by the gate outputcontrol circuit 500, the first pull-up transistor Tu1 of the first gateoutput buffer circuit GBUF1 and the second pull-up transistor Tu2 of thesecond gate output buffer circuit GBUF2 may be simultaneously turned onor turned off simultaneously.

The gate node of the first pull-down transistor Td1 and the gate node ofthe second pull-down transistor Td2 may be electrically connected. Thatis, the gate node of the first pull-down transistor Td1 and the gatenode of the second pull-down transistor Td2 may be commonly connected tothe QB node.

Therefore, by the voltage of the QB node controlled by the gate outputcontrol circuit 500, the first pull-down transistor Td1 of the firstgate output buffer circuit GBUF1 and the second pull-down transistor Td2of the second gate output buffer circuit GBUF2 are simultaneously turnedon or turned off simultaneously.

For example, when the gate driving circuit 130 performs gate driving in8 phases, the level shifter 300 may generate and output eight clocksignals CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, and CLK8. The gatedriving circuit 130 may perform gate driving using eight clock signalsCLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, and CLK8.

As in the previous example, when the gate driving circuit 130 performsgate driving in 8 phases and has a structure in which two gate outputbuffer circuits GBUF1 and GBUF2 share one Q node, as shown in FIG. 5,the odd-numbered clock signals CLK1, CLK3, CLK5, and CLK7 among theeight clock signals CLK1 to CLK8 may have the same signalcharacteristics, and may be respectively input to the first gate outputbuffer circuits GBUF1 connected to different Q nodes to be used togenerate gate signals. The even-numbered clock signals CLK2, CLK4, CLK6,and CLK8 among the eight clock signals CLK1 to CLK8 may have the samesignal characteristics, and may be respectively input to the second gateoutput buffer circuits GBUF2 connected to different Q nodes Q to be usedto generate gate signals.

Therefore, below, a representative clock signal of the odd-numberedclock signals CLK1, CLK3, CLK5, and CLK7 having the same signalcharacteristics will be described as a first clock signal CLK1. And arepresentative clock signal of the even-numbered clock signals CLK2,CLK4, CLK6, and CLK8 having the same signal characteristics is referredto as a second clock signal CLK2.

Meanwhile, in the display device 100 according to embodiments of thepresent disclosure, the gate driving circuit 130 may perform overlapgate driving.

When the gate driving circuit 130 performs overlap gate driving, a highlevel voltage section of each of the first and second clock signals CLK1and CLK2 may partially overlap. Accordingly, turn-on level voltagesections of the first gate signal Vgout1 and the second gate signalVgout2 corresponding to successive driving timings may partiallyoverlap. Here, the turn-on level voltage section of each of the firstgate signal Vgout1 and the second gate signal Vgout2 may be a high levelvoltage section or a low level voltage section. Hereinafter, forconvenience of description, the turn-on level voltage section of each ofthe first gate signal Vgout1 and the second gate signal Vgout2 will bedescribed as the high level voltage section.

When the gate driving circuit 130 performs the overlap gate driving, thehigh level voltage section of the first gate signal Vgout1 and the highlevel voltage section of the second gate signal Vgout2 may partiallyoverlap.

For example, each of the high level voltage section of the first gatesignal Vgout1 and the high level voltage section of the second gatesignal Vgout2 may have a temporal length of 2H. In this case, anoverlapping section in which the high level voltage section of the firstgate signal Vgout1 and the high level voltage section of the second gatesignal Vgout2 overlap may have a temporal length of 1H.

When the gate driving circuit 130 is of the GIP type and has a Q nodesharing structure, the size of the bezel area (non-display area NDA) ofthe display panel 110 may be reduced. In addition, when the gate drivingcircuit 130 performs the overlap gate driving, the charging time of thestorage capacitor Cst disposed in each of the plurality of sub-pixels SPmay be increased to improve image quality.

FIG. 6 is a diagram illustrating a characteristic deviation between gatesignals Vgout1 and Vgout2 output from the gate driving circuit 130 ofFIG. 5 according to one embodiment.

Referring to FIG. 6, the level shifter 300 may output the first clocksignal CLK1 and the second clock signal CLK2. Here, the first clocksignal CLK1 and the second clock signal CLK2 may have the same signalwaveform and signal characteristics. That is, a rising length CR1 of thefirst clock signal CLK1 and a rising length CR2 of the second clocksignal CLK2 may be equal, and a falling length CF1 of the first clocksignal CLK1 and a falling length CF2 of the second clock signal CLK2 maybe equal.

When the gate driving circuit 130 uses the first clock signal CLK1 andthe second clock signal CLK2 having the same signal waveform and signalcharacteristics, has a Q node sharing structure, and performs overlapgate driving, a signal waveform of the first gate signal Vgout1 outputfrom the gate driving circuit 130 may be different from a signalwaveform of the second gate signal Vgout2.

For example, a falling length F1 of the first gate signal Vgout1 and afalling length F2 of the second gate signal Vgout2 may be different fromeach other. The falling length described herein may be referred to as afalling time.

For another example, a rising length R1 of the first gate signal Vgout1and a rising length R2 of the second gate signal Vgout2 may be differentfrom each other. The rising length described herein may be referred toas a rising time.

The above-described deviation in output characteristics (risingcharacteristic deviation, falling characteristic deviation) between thefirst gate signal Vgout1 and the second gate signal Vgout2 may cause anoperation difference between transistors (e.g., SCT and SENT in FIG. 2B)to which the first gate signal Vgout1 and the second gate signal Vgout2are applied. Accordingly, image quality deterioration may be caused.

The display device 100 according to the embodiments of the presentdisclosure may obtain an effect of improving image quality by increasingthe charging time in each sub-pixel SP by performing overlap gatedriving, and may obtain an effect of reducing the size of the bezel area(non-display area NDA) of the display panel 110 through the Q nodesharing structure. The display device 100 according to the exemplaryembodiments of the present disclosure may provide a compensation methodcapable of reducing output characteristic deviation between gate signalsVgout1 and Vgout2 that may be caused through simultaneous application ofthe overlap gate driving and the Q node sharing structure. Hereinafter,this will be described in detail.

FIGS. 7A, 7B, and 7C are diagrams for explaining a characteristicdeviation compensation function between gate signals Vgout1 and Vgout2output from the gate driving circuit 130 of FIG. 5 according to oneembodiment.

Referring to FIGS. 7A to 7C, in order to compensate for thecharacteristic deviation between the gate signals, the level shifter 300may generate the first clock signal CLK1 and the second clock signalCLK2 by controlling at least one of a rising characteristic and afalling characteristic of at least one of the first clock signal CLK1and the second clock signal CLK2, and may output the generated firstclock signal CLK1 and the second clock signal CLK2.

Accordingly, the falling length CF1 of the first clock signal CLK1 andthe falling length CF2 of the second clock signal CLK2 may be differentfrom each other, or the rising length CR1 of the first clock signal CLK1and the rising length CR2 of the second clock signal CLK2 may bedifferent from each other.

Referring to FIG. 7A, the level shifter 300 may control the firstfalling length CF1 of the first clock signal CLK1 to be longer than thesecond falling length CF2 of the second clock signal CLK2 through thefalling control.

It will be described in more detail below. In FIG. 7A, the risingtimings of the first gate signal Vgout1 and the second gate signalVgout2 are the same, but this is only shown for convenience ofdescription. In reality, the first gate signal Vgout1 may be a gatesignal that rises first from a low level voltage to a high level voltagethan the second gate signal Vgout2, and falls first from a high levelvoltage to a low level voltage than the second gate signal Vgout2. Assuch, when the first gate signal Vgout1 may be a gate signal applied tothe gate line GL1 scanned before the second gate signal Vgout2, underthe Q node sharing structure, a phenomenon (falling characteristicdeviation in FIG. 6) in which the falling length F2 of the second gatesignal Vgout2 may be relatively longer than the falling length F1 of thefirst gate signal Vgout1 may occur. In order to solve the fallingcharacteristic deviation, the level shifter 300 intentionally lengthensthe falling length CF1 of the first clock signal CLK1, which is thebasis for generating the first gate signal Vgout1, so that the fallinglength F1 of the first gate signal Vgout1 may be intentionallylengthened. According to this falling control, the lengthened fallinglength F1 of the first gate signal Vgout1 may be equal to the originallylong falling length F2 of the second gate signal Vgout2.

When the falling control is performed through the clock control of thelevel shifter 300, the difference between the falling length F1 of thefirst gate signal Vgout1 and the falling length F2 of the second gatesignal Vgout2 may become smaller than the difference when the fallingcontrol is not performed.

By the falling control through the clock control of the level shifter300, the difference between the falling length F1 of the first gatesignal Vgout1 and the falling length F2 of the second gate signal Vgout2may become smaller than the difference between the falling length CF1 ofthe first clock signal CLK1 and the falling length CF2 of the secondclock signal CLK2.

According to the above-described falling control, the deviation in thefalling characteristics between the first and second gate signals Vgout1and Vgout2 is compensated, so that image quality can be improved.

Referring to FIG. 7B, the level shifter 300 may control the secondrising time CR2 of the second clock signal CLK2 to be longer than thefirst rising time CR1 of the first clock signal CLK1 through the risingcontrol.

It will be described in more detail below. In FIG. 7B, the first gatesignal Vgout1 may be a gate signal that rises first from a low levelvoltage to a high level voltage than the second gate signal Vgout2, andfalls first from a high level voltage to a low level voltage than thesecond gate signal Vgout2. As such, when the first gate signal Vgout1may be a gate signal applied to the gate line GL1 scanned before thesecond gate signal Vgout2, under the Q node sharing structure, aphenomenon (rising characteristic deviation in FIG. 6) in which therising length R1 of the first gate signal Vgout1 may be relativelylonger than the rising length R2 of the second gate signal Vgout2 mayoccur. In order to solve such a rising characteristic deviation, thelevel shifter 300 intentionally lengthens the rising length CR2 of thesecond clock signal CLK2, which is the basis for generating the secondgate signal Vgout2, so that the rising length R2 of the second gatesignal Vgout2 may be intentionally lengthened. According to this risingcontrol, the lengthened rising length R2 of the second gate signalVgout2 may be equal to the originally long rising length R1 of the firstgate signal Vgout1.

When the rising control is performed through the clock control of thelevel shifter 300, the difference between the rising length R1 of thefirst gate signal Vgout1 and the rising length R2 of the second gatesignal Vgout2 may become smaller than the difference when the risingcontrol is not performed.

By the rising control through the clock control of the level shifter 300described above, the difference between the rising length R1 of thefirst gate signal Vgout1 and the rising length R2 of the second gatesignal Vgout2 may become smaller than the difference between the risinglength CR2 of the second clock signal CLK2 and the rising length CR1 ofthe first clock signal CLK1.

According to the above-described rising control through the clockcontrol of the level shifter 300, the deviation in the risingcharacteristics between the first and second gate signals Vgout1 andVgout2 may be compensated, and image quality may be improved.

Referring to FIG. 7C, the level shifter 300 may control the firstfalling length CF1 of the first clock signal CLK1 to be longer than thesecond falling length CF2 of the second clock signal CLK2 through thefalling control. In addition, the level shifter 300 may control thesecond rising time CR2 of the second clock signal CLK2 to be longer thanthe first rising time CR1 of the first clock signal CLK1 through therising control.

As the falling control and the rising control are performed through theclock control by the level shifter 300, the falling length CF1 of thefirst clock signal CLK1 may be longer than the falling length CF2 of thesecond clock signal CLK2, and the rising length CR2 of the second clocksignal CLK2 may be longer than the rising length CR1 of the first clocksignal CLK1.

As the falling control and the rising control are performed through theclock control by the level shifter 300, the difference between thefalling length F1 of the first gate signal Vgout1 and the falling lengthF2 of the second gate signal Vgout2 may be smaller than the differencewhen the falling control is not performed. Furthermore, the differencebetween the rising length R1 of the first gate signal Vgout1 and therising length R2 of the second gate signal Vgout2 may be smaller than adifference when the rising control is not performed.

As the falling control and the rising control are performed through theclock control by the level shifter 300, the difference between thefalling length F1 of the first gate signal Vgout1 and the falling lengthF2 of the second gate signal Vgout2 may be smaller than the differencebetween the falling length CF1 of the first clock signal CLK1 and thefalling length CF2 of the second clock signal CLK2. Furthermore, thedifference between the rising length R1 of the first gate signal Vgout1and the rising length R2 of the second gate signal Vgout2 may be smallerthan the difference between the rising length CR2 of the second clocksignal CLK2 and the rising length CR1 of the first clock signal CLK1.

As the falling control and the rising control are performed through theclock control by the level shifter 300, both the rising characteristicdeviation and the falling characteristic deviation between the first andsecond gate signals Vgout1 and Vgout2 are compensated, so that imagequality can be greatly improved.

Hereinafter, the level shifter 300 for compensating for a deviation inoutput characteristics between the first and second gate signals Vgout1and Vgout2 will be described in more detail.

FIG. 8 is a level shifter 300 according to embodiments of the presentdisclosure. FIG. 9 is a driving timing diagram for the level shifter 300according to embodiments of the present disclosure.

Referring to FIG. 8, the level shifter 300 according to embodiments ofthe present disclosure may include: input terminals Ph, Pl, Pm, Pgclk,and Pmclk; output terminals Pclk1 and Pclk2; a first clock outputcircuit COC1 for outputting the first clock signal CLK1; a second clockoutput circuit COC2 for outputting the second clock signal CLK2; and aclock control circuit 800 for controlling the first clock output circuitCOC1 and the second clock output circuit COC2.

Referring to FIG. 8, the input terminals Ph, Pl, Pm, Pgclk, and Pmclkmay include a high input terminal Ph to which high level voltage VGH isinput, a low input terminal Pl to which a low level voltage VGL isinput, and an intermediate input terminal Pm to which the intermediatelevel voltage AVDD is input.

The high input terminal Ph, the low input terminal Pl, and theintermediate input terminal Pm may be electrically connected to thepower management integrated circuit 310 that supplies the intermediatelevel voltage AVDD. A resistor Rm may be connected between theintermediate input terminal Pm and the power management integratedcircuit 310.

Referring to FIG. 9, among the high level voltage VGH, the low levelvoltage VGL, and the intermediate level voltage AVDD, the high levelvoltage VGH may be the highest voltage (e.g., largest voltage) and thelow level voltage VGL may be the lowest voltage (e.g., smallestvoltage). Among the high level voltage VGH, the low level voltage VGL,and the intermediate level voltage AVDD, the intermediate level voltageAVDD may be greater than the low level voltage VGL and less than thehigh level voltage VGH. The intermediate level voltage AVDD may be acenter voltage at the center of the high level voltage VGH and the lowlevel voltage VGL, or a voltage higher or lower than the center voltage.

Referring to FIG. 9, the high level voltage VGH input to the high inputterminal Ph may be a high level voltage of each of the first clocksignal CLK1 and the second clock signal CLK2. The low level voltage VGLinput to the low input terminal Pl may be a low level voltage of each ofthe first clock signal CLK1 and the second clock signal CLK2.

Referring to FIG. 9, while the first clock signal CLK1 rises, thevoltage of the first clock signal CLK1 may be changed from the low levelvoltage VGL to the high level voltage VGH through the middle levelvoltage AVDD. While the second clock signal CLK2 rises, the voltage ofthe second clock signal CLK2 may be changed from the low level voltageVGL to the high level voltage VGH through the middle level voltage AVDD.

Referring to FIG. 9, while the first clock signal CLK1 falls, thevoltage of the first clock signal CLK1 may be changed from the highlevel voltage VGH to the low level voltage VGL through the middle levelvoltage AVDD. While the second clock signal CLK2 falls, the voltage ofthe second clock signal CLK2 may be changed from the high level voltageVGH to the low level voltage VGL through the middle level voltage AVDD.

Referring to FIG. 8, the input terminals Ph, Pl, Pm, Pgclk, and Pmclkmay further include a generation clock terminal Pgclk to which ageneration clock signal GCLK is input and a modulation clock terminalPmclk to which a modulation clock signal MCLK is input.

The generation clock terminal Pgclk and the modulation clock terminalPmclk may be electrically connected to the controller 140. That is, thelevel shifter 300 may receive the generation clock signal GCLK and themodulation clock signal MCLK from the controller 140.

Referring to FIG. 8, the output terminals Pclk1 and Pclk2 may include afirst output terminal Pclk1 outputting the first clock signal CLK1 and asecond output terminal Pclk2 outputting the second clock signal CLK2.Here, the first output terminal Pclk1 and the second output terminalPclk2 may be electrically connected to the gate driving circuit 130.

Referring to FIG. 8, the first clock output circuit COC1 may include afirst rising switch S1 r for controlling the electrical connectionbetween the high input terminal Ph and the first output terminal Pclk1,a first falling switch S1 f for controlling the electrical connectionbetween the low input terminal Pl and the first output terminal Pclk1,and a first gate pulse modulation switch GPMS1 for controlling anelectrical connection between the intermediate input terminal Pm and thefirst output terminal Pclk1.

Referring to FIG. 8, the second clock output circuit COC2 may include asecond rising switch S2 r for controlling the electrical connectionbetween the high input terminal Ph and the second output terminal Pclk2,a second falling switch S2 f for controlling the electrical connectionbetween the low input terminal Pl and the second output terminal Pclk2,and a second gate pulse modulation switch GPMS2 for controlling anelectrical connection between the intermediate input terminal Pm and thesecond output terminal Pclk2.

Each of the first rising switch S1 r, the first falling switch S1 f, thefirst gate pulse modulation switch GPMS1, the second rising switch S2 r,the second falling switch S2 f, and the second gate pulse modulationswitch GPMS2 may be implemented as an n-type transistor or a p-typetransistor.

Referring to FIG. 8, the clock control circuit 800 may control theswitching operation (on-off operation) of each of the first risingswitch S1 r, the first falling switch S1 f, the first gate pulsemodulation switch GPMS1, the second rising switch S2 r, the secondfalling switch S2 f, and the second gate pulse modulation switch GPMS2.

To this end, the clock control circuit 800 may output a first risingcontrol signal C1 r for controlling the switching operation of the firstrising switch S1 r, a first falling control signal C1 f for controllingthe switching operation of the first falling switch S1 f, and a firstintermediate control signal CM1 for controlling a switching operation ofthe first gate pulse modulation switch GPMS1. And the clock controlcircuit 800 may output a second rising control signal C2 r forcontrolling the switching operation of the second rising switch S2 r, asecond falling control signal C2 f for controlling the switchingoperation of the second falling switch S2 f, and a second intermediatecontrol signal CM2 for controlling a switching operation of the secondgate pulse modulation switch GPMS2.

Meanwhile, each of the first gate pulse modulation switch GPMS1, thefirst rising switch S1 r, the first falling switch S1 f, the second gatepulse modulation switch GPMS2, the second rising switch S2 r and thesecond falling switch S2 f may have an on-resistance. Here, theon-resistance of the switch is a resistance that prevents the flow ofcurrent flowing through the switch when a control signal (gate voltage)capable of turning on the switch is applied to the switch.

The on-resistance Ron1 of the first gate pulse modulation switch GPMS1may be greater than the on-resistance of each of the first rising switchS1 r and the first falling switch S1 f. Accordingly, the switching speedof the first gate pulse modulation switch GPMS1 may be slower than theswitching speed of each of the first rising switch S1 r and the firstfalling switch S1 f.

The on-resistance Ron2 of the second gate pulse modulation switch GPMS2may be greater than the on-resistance of each of the second risingswitch S2 r and the second falling switch S2 f. Accordingly, theswitching speed of the second gate pulse modulation switch GPMS2 may beslower than the switching speed of each of the second rising switch S2 rand the second falling switch S2 f.

In the level shifter 300 according to embodiments of the presentdisclosure, each of the on-resistance Ron1 of the first gate pulsemodulation switch GPMS1 and the on-resistance Ron2 of the first gatepulse modulation switch GPMS2 may be independently adjusted.

In addition, in the level shifter 300 according to embodiments of thepresent disclosure, each of the on-resistance of the first fallingswitch S1 f and the on-resistance of the second rising switch S2 r maybe independently adjusted.

In addition, in the level shifter 300 according to embodiments of thepresent disclosure, each of the on-resistance of the first rising switchS1 r and the on-resistance of the second falling switch S2 f may beindependently adjusted.

The level shifter 300 according to embodiments of the present disclosuremay further include the first gate pulse modulation switch GPMS1associated with the generation of the first clock signal CLK1, and thesecond gate pulse modulation switch GPMS2 associated with the generationof the second clock signal CLK2. In this respect, the level shifter 300according to embodiments of the present disclosure has a unique feature.

Referring to FIGS. 8 and 9, the generation clock signal GCLK may includemultiple pulses g1, g2, g3, g4, g5, etc., and the modulation clocksignal MCLK may include a plurality of pulses m1, m2, etc.

Referring to FIGS. 8 and 9, the clock control circuit 800 may controloperation timings of the first clock output circuit COC1 and the secondclock output circuit COC2 based on the generation clock signal GCLK andthe modulation clock signal MCLK. Accordingly, the clock control circuit800 may control the generation and output of the first clock signal CLK1and the second clock signal CLK2 having a desired signal waveform.Accordingly, the first clock output circuit COC1 and the second clockoutput circuit COC2 may output the first clock signal CLK1 and thesecond clock signal CLK2 having a desired signal waveform.

Referring to FIGS. 8 and 9, the clock control circuit 800 may output thefirst rising control signal C1 r, the first falling control signal C1 f,and the first intermediate control signal CM1 to the first clock outputcircuit COC1, based on a first pulse g1 of the generation clock signalGCLK and a first pulse m1 of the modulation clock signal MCLK. The firstrising control signal C1 r is a control signal for controlling on-off ofthe first rising switch S1 r included in the first clock output circuitCOC1. The first falling control signal C1 f is a control signal forcontrolling on-off of the first falling switch S1 f included in thefirst clock output circuit COC1. The first intermediate control signalCM1 is a control signal for controlling on-off of the first gate pulsemodulation switch GPMS1 included in the first clock output circuit COC1.Accordingly, the first clock output circuit COC1 may generate and outputthe first clock signal CLK1 having a desired signal waveform.

Referring to FIGS. 8 and 9, the clock control circuit 800 may output thesecond rising control signal C2 r, the second falling control signal C2f, and the second intermediate control signal CM2 to the second clockoutput circuit COC2, based on a second pulse g2 of the generation clocksignal GCLK and a second pulse m2 of the modulation clock signal MCLK.The second rising control signal C2 r is a control signal forcontrolling on-off of the second rising switch S2 r included in thesecond clock output circuit COC2. The second falling control signal C2 fis a control signal for controlling on-off of the second falling switchS2 f included in the second clock output circuit COC2. The secondintermediate control signal CM2 is a control signal for controllingon-off of the second gate pulse modulation switch GPMS2 included in thesecond clock output circuit COC2. Accordingly, the second clock outputcircuit COC2 may generate and output the second clock signal CLK2 havinga desired signal waveform.

Hereinafter, a process of generating the first clock signal CLK1 and thesecond clock signal CLK2 will be described with reference to FIGS. 8 and9. However, FIG. 9 shows the first clock signal CLK1 and the secondclock signal CLK2 generated without a control process (falling control,rising control). In order to describe the generation of the first clocksignal CLK1 and the second clock signal CLK2 when there is no controlprocess, it is assumed that the on-resistance Ron1 of the first gatepulse modulation switch GPMS1 and the on-resistance Ron2 of the secondgate pulse modulation switch GPMS2 are equal to each other and areconstant without changing with time.

First, the generation of the first clock signal CLK1 will be described.

Rising of the first clock signal CLK1 may proceed in two steps. The twosteps may include a first rising step R-STEP1 and a second rising stepR-STPE2.

The first rising step R-STEP1 may be a step in which the voltage of thefirst clock signal CLK1 is changed from the low level voltage VGL to theintermediate level voltage AVDD by the first gate pulse modulationswitch GPMS1.

The first rising step R-STEP1 may be started when the rising time of thefirst pulse g1 of the generation clock signal GCLK starts, and mayproceed during the pulse period Wg of the first pulse g1 of thegeneration clock signal GCLK.

When the rising time of the first pulse g1 of the generation clocksignal GCLK comes, the first gate pulse modulation switch GPMS1 may beturned on. During the pulse period corresponding to the pulse width Wgof the generation clock signal GCLK, the intermediate level voltage AVDDmay be applied to the first output terminal Pclk1 through the turned-onfirst gate pulse modulation switch GPMS1. Before the intermediate levelvoltage AVDD is applied, the first output terminal Pclk1 may be in astate in which the low level voltage VGL is applied.

Since the on-resistance Ron1 of the first gate pulse modulation switchGPMS1 is large, the voltage of the first output terminal Pclk1 may notrapidly rise from the low level voltage VGL to the intermediate levelvoltage AVDD. The time it takes for the voltage of the first outputterminal Pclk1 to rise to the intermediate level voltage AVDD may be aperiod corresponding to the pulse width Wg of the generation clocksignal GCLK.

The second rising step R-STEP2 may be performed following the firstrising step R-STEP1. The second rising step R-STEP2 may be a step inwhich the voltage of the first clock signal CLK1 is changed from theintermediate level voltage AVDD to the high level voltage VGH by thefirst rising switch S1 r.

The second rising step R-STEP2 may be started when the falling time ofthe first pulse g1 of the generation clock signal GCLK starts.

The first rising switch S1 r may be turned on when the falling time ofthe first pulse g1 of the generation clock signal GCLK starts.Accordingly, the high level voltage VGH may be applied to the firstoutput terminal Pclk1 through the turned-on first rising switch S1 r.Before the high level voltage VGH is applied, the first output terminalPclk1 may be in a state in which the intermediate level voltage AVDD isapplied.

The on-resistance of the first rising switch S1 r may be smaller thanthe on-resistance Ron1 of the first gate pulse modulation switch GPMS1.Accordingly, when the first rising switch S1 r is turned on, the voltageof the first output terminal Pclk1 may rapidly increase from theintermediate level voltage AVDD to the high level voltage VGH. A voltagerising slope (voltage rising rate) of the first output terminal Pclk1 inthe second rising step R-STEP2 may be steeper (greater) than a voltagerising slope (voltage rising rate) of the first output terminal Pclk1 inthe first rising step R-STEP1.

After the first output terminal Pclk1 is changed to the high levelvoltage VGH, the first rising switch S1 r may maintain the turn-on stateuntil the falling start time of the first clock signal CLK1 is reached.Accordingly, the first output terminal Pclk1 may maintain the high levelvoltage VGH until the falling start time of the first clock signal CLK1occurs.

After the first clock signal CLK1 rises by the first pulse g1 of thegeneration clock signal GCLK, when the rising time of the first pulse m1of the modulation clock signal MCLK comes, the falling of the firstclock signal CLK1 may start. Here, the first pulse g1 among theplurality of pulses g1, g2, and etc. included in the generation clocksignal GCLK may be a pulse triggering the rising of the first clocksignal CLK1. The first pulse m1 among the plurality of pulses m1, m2,and etc. included in the modulation clock signal MCLK may be a pulsetriggering the falling of the first clock signal CLK1. In this sense,the first pulse g1 of the generation clock signal GCLK and the firstpulse m1 of the modulation clock signal MCLK may be related to eachother and involved in the generation (rising, falling) of the same firstclock signal CLK1.

The rising length CR1 of the first clock signal CLK1 may be the sum ofthe temporal length Wg of the first rising step R-STEP1 and the temporallength of the second rising step R-STEP2.

The falling of the first clock signal CLK1 may also proceed in twosteps. The two steps may include a first falling step F-STEP1 and asecond falling step F-STEP2.

The first falling step F-STEP1 may be a step in which the voltage of thefirst clock signal CLK1 is changed from the high level voltage VGH tothe intermediate level voltage AVDD by the first gate pulse modulationswitch GPMS1.

The first falling step F-STEP1 may start at the rising time of the firstpulse m1 of the modulation clock signal MCLK, and may proceed during thepulse period Wm of the first pulse m1 of the modulation clock signalMCLK.

When the rising time of the first pulse m1 of the modulation clocksignal MCLK comes, the first gate pulse modulation switch GPMS1 may beturned on. During the pulse period corresponding to the pulse width Wmof the modulation clock signal MCLK, the intermediate level voltage AVDDmay be applied to the first output terminal Pclk1 through the turned-onfirst gate pulse modulation switch GPMS1. Before the intermediate levelvoltage AVDD is applied, the first output terminal Pclk1 may be in astate in which the high level voltage VGH is applied.

Since the on-resistance Ron1 of the first gate pulse modulation switchGPMS1 is large, the voltage of the first output terminal Pclk1 may notrapidly fall from the high level voltage VGH to the middle level voltageAVDD. The time taken for the voltage of the first output terminal Pclk1to fall to the intermediate level voltage AVDD may be a periodcorresponding to the pulse width Wm of the modulation clock signal MCLK.

Following the first falling step F-STEP1, the second falling stepF-STEP2 may proceed. The second falling step F-STEP2 may be a step inwhich the voltage of the first clock signal CLK1 is changed from theintermediate level voltage AVDD to the low level voltage VGL by thefirst falling switch S1 f.

The second falling step F-STEP2 may be started when the falling time ofthe first pulse m1 of the modulation clock signal MCLK starts.

When the falling time of the first pulse m1 of the modulation clocksignal MCLK comes, the first falling switch S1 f may be turned on.Accordingly, the low level voltage VGL may be applied to the firstoutput terminal Pclk1 through the turned-on first falling switch S1 f.Before the low level voltage VGL is applied, the first output terminalPclk1 may be in a state in which the intermediate level voltage AVDD isapplied.

The on-resistance of the first falling switch S1 f may be smaller thanthe on-resistance Ron1 of the first gate pulse modulation switch GPMS1.Accordingly, when the first falling switch S1 f is turned on, thevoltage of the first output terminal Pclk1 may be rapidly lowered fromthe intermediate level voltage AVDD to the low level voltage VGL. Avoltage falling slope (voltage falling rate) of the first outputterminal Pclk1 in the second polling step F-STEP2 may be steeper(greater) than a voltage falling slope (voltage falling rate) of thefirst output terminal Pclk1 in the first polling step F-STEP1.

The falling length CF1 of the first clock signal CLK1 may be the sum ofthe temporal length Wm of the first falling step F-STEP1 and thetemporal length of the second falling step F-STEP2.

Next, generation of the second clock signal CLK2 will be described.

Rising of the second clock signal CLK2 may proceed in two steps. The twosteps may include a first rising step R-STEP1 and a second rising stepR-STEP2.

The first rising step R-STEP1 may be a step in which the voltage of thesecond clock signal CLK2 is changed from the low level voltage VGL tothe intermediate level voltage AVDD by the second gate pulse modulationswitch GPMS2.

The first rising step R-STEP1 may be started when the rising time of thesecond pulse g2 of the generation clock signal GCLK starts, and mayproceed during the pulse period Wg of the second pulse g2 of thegeneration clock signal GCLK.

When the rising time of the second pulse g2 of the generation clocksignal GCLK comes, the second gate pulse modulation switch GPMS2 may beturned on. During the pulse period corresponding to the pulse width Wgof the generation clock signal GCLK, the intermediate level voltage AVDDmay be applied to the second output terminal Pclk2 through the turned-onsecond gate pulse modulation switch GPMS2. Before the intermediate levelvoltage AVDD is applied, the second output terminal Pclk2 may be in astate in which the low level voltage VGL is applied.

Since the on-resistance Ron2 of the second gate pulse modulation switchGPMS2 is large, the voltage of the second output terminal Pclk2 may notrapidly rise from the low level voltage VGL to the intermediate levelvoltage AVDD. The time taken for the voltage of the second outputterminal Pclk2 to rise to the intermediate level voltage AVDD may be aperiod corresponding to the pulse width Wg of the generation clocksignal GCLK.

Following the first rising step R-STEP1, the second rising step R-STEP2may be performed. The second rising step R-STEP2 may be a step in whichthe voltage of the second clock signal CLK2 is changed from theintermediate level voltage AVDD to the high level voltage VGH by thesecond rising switch S2 r.

The second rising step R-STEP2 may be started when the falling time ofthe second pulse g2 of the generation clock signal GCLK starts.

When the falling time of the second pulse g2 of the generation clocksignal GCLK comes, the second rising switch S2 r may be turned on.Accordingly, the high level voltage VGH may be applied to the secondoutput terminal Pclk2 through the turned-on second rising switch S2 r.Before the high level voltage VGH is applied, the second output terminalPclk2 may be in a state in which the intermediate level voltage AVDD isapplied.

The on-resistance of the second rising switch S2 r may be smaller thanthe on-resistance Ron2 of the second gate pulse modulation switch GPMS2.Accordingly, when the second rising switch S2 r is turned on, thevoltage of the second output terminal Pclk2 may rapidly increase fromthe intermediate level voltage AVDD to the high level voltage VGH. Avoltage falling slope (voltage falling rate) of the second outputterminal Pclk2 in the second polling step F-STEP2 may be steeper(greater) than a voltage falling slope (voltage falling rate) of thesecond output terminal Pclk2 in the first polling step F-STEP1.

After being changed to the high level voltage VGH, the second outputterminal Pclk2 may maintain the high level voltage VGH until the fallingstart time.

The rising length CR2 of the second clock signal CLK2 may be the sum ofthe temporal length Wg of the first rising step R-STEP1 and the temporallength of the second rising step R-STEP2.

The falling of the second clock signal CLK2 may also proceed in twosteps. The two steps may include a first falling step F-STEP1 and asecond falling step F-STEP2.

The first falling step F-STEP1 may be started when the rising time ofthe second pulse m2 of the modulation clock signal MCLK starts. When thefirst falling step F-STEP1 starts, the falling of the second clocksignal CLK2 may start. Here, the second pulse g2 among the plurality ofpulses g1, g2, etc. included in the generation clock signal GCLK may bea pulse that triggers the rising of the second clock signal CLK2. Thesecond pulse m2 among the plurality of pulses m1, m2, etc. included inthe modulation clock signal MCLK may be a pulse that triggers thefalling of the second clock signal CLK2. In this sense, the second pulseg2 of the generation clock signal GCLK and the second pulse m2 of themodulation clock signal MCLK may be related to each other and involvedin generation (rising, falling) of the same second clock signal CLK2.

The first falling step F-STEP1 may be a step in which the voltage of thesecond clock signal CLK2 is changed from the high level voltage VGH tothe intermediate level voltage AVDD by the second gate pulse modulationswitch GPMS2.

The first falling step F-STEP1 may be started when the rising time ofthe second pulse m2 of the modulation clock signal MCLK starts, and mayproceed during the pulse period Wm of the second pulse m2 of themodulation clock signal MCLK.

When the rising time of the second pulse m2 of the modulation clocksignal MCLK comes, the second gate pulse modulation switch GPMS2 may beturned on. During the pulse period corresponding to the pulse width Wmof the modulation clock signal MCLK, the intermediate level voltage AVDDmay be applied to the second output terminal Pclk2 through the turned-onsecond gate pulse modulation switch GPMS2. Before the intermediate levelvoltage AVDD is applied, the second output terminal Pclk2 may be in astate in which the high level voltage VGH is applied.

Since the on-resistance Ron2 of the second gate pulse modulation switchGPMS2 is large, the voltage of the second output terminal Pclk2 may notrapidly fall from the high level voltage VGH to the intermediate levelvoltage AVDD. The time taken for the voltage of the second outputterminal Pclk2 to fall to the intermediate level voltage AVDD may be aperiod corresponding to the pulse width Wm of the modulation clocksignal MCLK.

The second falling step F-STEP2 may be a step in which the voltage ofthe second clock signal CLK2 is changed from the intermediate levelvoltage AVDD to the low level voltage VGL by the second falling switchS2 f.

The second falling step F-STEP2 may be started when the falling time ofthe second pulse m2 of the modulation clock signal MCLK starts.

When the falling timing of the second pulse m2 of the modulation clocksignal MCLK comes, the second falling switch S2 f may be turned on.Accordingly, the low level voltage VGL may be applied to the secondoutput terminal Pclk2 through the turned-on second falling switch S2 f.Before the low level voltage VGL is applied, the second output terminalPclk2 may be in a state in which the intermediate level voltage AVDD isapplied.

The on-resistance of the second falling switch S2 f may be smaller thanthe on-resistance Ron2 of the second gate pulse modulation switch GPMS2.Accordingly, when the second falling switch S2 f is turned on, thevoltage of the second output terminal Pclk2 may be rapidly lowered fromthe intermediate level voltage AVDD to the low level voltage VGL. Avoltage falling slope (voltage falling rate) of the second outputterminal Pclk2 in the second polling step F-STEP2 may be steeper(greater) than a voltage falling slope (voltage falling rate) of thesecond output terminal Pclk2 in the first polling step F-STEP1.

The falling length CF2 of the second clock signal CLK2 may be the sum ofthe temporal length Wm of the first falling step F-STEP1 and thetemporal length of the second falling step F-STEP2.

As described above, the driving timing diagram of FIG. 9 is for a casein which clock control (polling control and rising control) is notperformed by the level shifter 300 according to embodiments of thepresent disclosure. That is, in the driving timing diagram of FIG. 9, itis assumed that the on-resistance Ron1 of the first gate pulsemodulation switch GPMS1 and the on-resistance Ron2 of the second gatepulse modulation switch GPMS2 are the same and do not change with timeand are constant.

When clock control is not performed by the level shifter 300, the signalwaveform and signal characteristic of the first clock signal CLK1 andthe signal waveform and signal characteristic of the second clock signalCLK2 may be identical to each other. That is, the falling length CF1 ofthe first clock signal CLK1 may be equal to the falling length CF2 ofthe second clock signal CLK2, and the rising length CR2 of the secondclock signal CLK2 may be equal to the rising length CR1 of the firstclock signal CLK1.

According to embodiments of the present disclosure, the level shifter300 may perform clock control to compensate the output deviation of thegate driving circuit 130.

According to the clock control of the level shifter 300 performed tocompensate the output deviation of the gate driving circuit 130, thesignal waveform and signal characteristic of the first clock signal CLK1and the signal waveform and signal characteristic of the second clocksignal CLK2 may be different from each other. For example, the fallinglength CF1 of the first clock signal CLK1 may be different from thefalling length CF2 of the second clock signal CLK2, and/or the risinglength CR2 of the second clock signal CLK2 may be different from therising length CR1 of the first clock signal CLK1.

In order to reduce a deviation in the falling characteristics betweenthe first gate signal Vgout1 and the second gate signal Vgout2, thelevel shifter 300 may control the falling characteristics of the firstclock signal CLK1.

When controlling the falling characteristic of the first clock signalCLK1, the level shifter 300 may control the falling length CF1 of thefirst clock signal CLK1 to be longer than before the clock control(falling characteristic control). In this case, the falling length CF1of the first clock signal CLK1 may be longer than the falling length CF2of the second clock signal CLK2.

As the falling length CF1 of the first clock signal CLK1 increases, thefalling length F1 of the first gate signal Vgout1 may increase.Accordingly, the falling length F1 of the first gate signal Vgout1,which is increased according to the clock control, may be equal to orsimilar to the falling length F2 of the second gate signal Vgout2, whichwas originally long.

As described above, the difference between the falling length F1 of thefirst gate signal Vgout1 and the falling length F2 of the second gatesignal Vgout2 may be reduced or eliminated. Accordingly, the differencebetween the falling length F1 of the first gate signal Vgout1 and thefalling length F2 of the second gate signal Vgout2 may be smaller thanthe difference between the falling length CF1 of the first clock signalCLK1 and the falling length CF2 of the second clock signal CLK2.

The level shifter 300 may use one or more of two options to performclock control so that the falling length CF1 of the first clock signalCLK1 is longer than the falling length CF2 of the second clock signalCLK2. The two options may include a first option for adjusting theon-resistance Ron1 of the first gate pulse modulation switch GPMS1 inthe first falling step F-STEP1, and a second option for adjusting theon-resistance of the first falling switch S1 f in the second fallingstep F-STEP2.

In order to reduce a deviation in the rising characteristic between thefirst gate signal Vgout1 and the second gate signal Vgout2, the levelshifter 300 may control the rising characteristic of the second clocksignal CLK2.

When controlling the rising characteristic of the second clock signalCLK2, the level shifter 300 may control the rising length CR2 of thesecond clock signal CLK2 to be longer than before the clock control(rising characteristic control). In this case, the rising length CR2 ofthe second clock signal CLK2 may be longer than the rising length CR1 ofthe first clock signal CLK1.

Due to the increased rising length CR2 of the second clock signal CLK2,the rising length R2 of the second gate signal Vgout2 may be increased.Accordingly, the increased rising length R2 of the second gate signalVgout2 may be equal to or similar to the originally long falling lengthR1 of the first gate signal Vgout1.

As described above, the difference between the rising length R1 of thefirst gate signal Vgout1 and the rising length R2 of the second gatesignal Vgout2 may be reduced or eliminated. Accordingly, the differencebetween the rising length R1 of the first gate signal Vgout1 and therising length R2 of the second gate signal Vgout2 may be smaller thanthe difference between the rising length CR1 of the first clock signalCLK1 and the rising length CR2 of the second clock signal CLK2.

The level shifter 300 may use one or more of the two options to performclock control so that the rising length CR2 of the second clock signalCLK2 is longer than the rising length CR1 of the first clock signalCLK1. The two options may include a first option for adjusting theon-resistance Ron2 of the second gate pulse modulation switch GPMS2 inthe first rising step R-STEP1, and a second option for adjusting theon-resistance of the second rising switch S2 r in the second rising stepR-STEP2.

Below, the falling control of the first clock signal CLK1 of the levelshifter 300 will be described in more detail with reference to FIGS. 10,11A and 11B, and the rising control of the second clock signal CLK2 ofthe level shifter 300 will be described in more detail with reference toFIGS. 12, 13A and 13B.

FIG. 10 is a driving timing diagram for explaining two options forfalling control of a first clock signal CLK1 of the level shifter 300according to embodiments of the present disclosure. FIG. 11A is adriving timing diagram illustrating a first option for falling controlof the first clock signal CLK1 of the level shifter 300 according toembodiments of the present disclosure. FIG. 11B is a driving timingdiagram illustrating a second option for falling control of the firstclock signal CLK1 of the level shifter 300 according to embodiments ofthe present disclosure.

FIG. 10 shows the first clock signal CLK1 generated without fallingcontrol, FIG. 11A shows the first clock signal CLK1 generated by fallingcontrol according to the first option, and FIG. 11B shows the firstclock signal CLK1 generated by falling control according to the secondoption.

Referring to FIG. 10, the generation process of the first clock signalCLK1 by the level shifter 300 may include a rising step and a fallingstep. In the rising step, the level shifter 300 may increase the voltageof the first clock signal CLK1 in two steps (the first rising stepR-STEP1, the second rising step R-STEP2) using the first gate pulsemodulation switch GPMS1 and the first rising switch S1 r based on thefirst pulse g1 of the generation clock signal GCLK. In the falling step,the level shifter 300 may make the voltage of the first clock signalCLK1 fall in two steps (the first falling step F-STEP1, the secondfalling step F-STEP2) using the first gate pulse modulation switch GPMS1and the first falling switch S1 f based on the first pulse m1 of themodulation clock signal MCLK.

Referring to FIG. 10, the rising of the first clock signal CLK1 may beperformed in two steps R-STEP1 and R-STEP2, and the first gate pulsemodulation switch GPMS1 may be turned on before the first rising switchS1 r. Furthermore, the falling of the first clock signal CLK1 may beperformed in two steps F-STEP1 and F-STEP2), and the first gate pulsemodulation switch GPMS1 may be turned on before the first falling switchS1 f.

The level shifter 300 may use one or more of the two options to performclock control so that the falling length CF1 of the first clock signalCLK1 becomes longer than the falling length CF2 of the second clocksignal CLK2. The two options may include a first option for adjustingthe on-resistance Ron1 of the first gate pulse modulation switch GPMS1in the first falling step F-STEP1, and a second option for adjusting theon-resistance of the first falling switch S1 f in the second fallingstep F-STEP2.

Referring to FIG. 11A, in order to perform the first option by the levelshifter 300, the on-resistance Ron1 of the first gate pulse modulationswitch GPMS1 when the first clock signal CLK1 rises and theon-resistance Ron1 of the first gate pulse modulation switch GPMS1 whenthe first clock signal CLK1 falls may be independently adjusted.

For example, the on-resistance Ron1 of the first gate pulse modulationswitch GPMS1 when the first clock signal CLK1 falls may be adjusted tobe greater than the on-resistance Ron1 of the first gate pulsemodulation switch GPMS1 when the first clock signal CLK1 rises.

Referring to FIG. 11A, for the first option of making the falling lengthCF1 of the first clock signal CLK1 longer than the falling length CF2 ofthe second clock signal CLK2, the on-resistance Ron1 of the first gatepulse modulation switch GPMS1 when the first clock signal CLK1 falls maybe adjusted to be greater than the on-resistance Ron2 of the second gatepulse modulation switch GPMS2 when the second clock signal CLK2 falls.

Referring to FIG. 11A, in the first falling step F-STEP1, since theon-resistance Ron1 of the first gate pulse modulation switch GPMS1involved in the falling of the first clock signal CLK1 is largelyadjusted, during the period Wm of the first falling step F-STEP1, thevoltage of the first clock signal CLK1 may not fall from the high levelvoltage VGH to the intermediate level voltage AVDD.

Therefore, in the second falling step F-STEP2, even if the on-resistanceof the first falling switch S1 f involved in the falling of the firstclock signal CLK1 is not adjusted, since the voltage of the first clocksignal CLK1 starts to fall from a voltage higher than the intermediatelevel voltage AVDD, it takes longer for the voltage of the first clocksignal CLK1 to fall to the low level voltage VGL. Accordingly, by thefalling control, the falling length CF1 of the first clock signal CLK1can become longer. The falling length CF1 of the first clock signal CLK1made longer by the falling control can be longer than the falling lengthCF1 of the first clock signal CLK1 when there is no falling control asshown in FIG. 10.

Referring to FIG. 11B, in order to perform the second option by thelevel shifter 300, the on-resistance of the first falling switch S1 fmay be adjusted at the timing at which the first clock signal CLK1falls.

Referring to FIG. 11B, for the second option of making the fallinglength CF1 of the first clock signal CLK1 longer than the falling lengthCF2 of the second clock signal CLK2, the on-resistance of the firstfalling switch S1 f when the first clock signal CLK1 falls may beadjusted to be greater than the on-resistance of the second fallingswitch S2 f when the second clock signal CLK2 falls.

Referring to FIG. 11B, in the first falling step F-STEP1, since theon-resistance Ron1 of the first gate pulse modulation switch GPMS1involved in the falling of the first clock signal CLK1 is not adjusted,during the period Wm of the first falling phase F-STEP1, the voltage ofthe first clock signal CLK1 can fall from the high level voltage VGH tothe intermediate level voltage AVDD.

However, in the second falling step F-STEP2, since the on-resistance ofthe first falling switch S1 f involved in the falling of the first clocksignal CLK1 is largely adjusted, the voltage of the first clock signalCLK1 may decrease slowly. Accordingly, it may take a long time for thevoltage of the first clock signal CLK1 to drop to the low level voltageVGL. Accordingly, the falling length CF1 of the first clock signal CLK1becomes longer than in the case where there is no falling control asshown in FIG. 10.

FIG. 12 is a driving timing diagram for explaining two options forrising control of a second clock signal CLK2 of the level shifter 300according to embodiments of the present disclosure. FIG. 13A is adriving timing diagram illustrating a first option for rising control ofthe second clock signal CLK2 of the level shifter 300 according toembodiments of the present disclosure. FIG. 13B is a driving timingdiagram illustrating a second option for rising control of the secondclock signal CLK2 of the level shifter 300 according to embodiments ofthe present disclosure.

FIG. 12 shows the second clock signal CLK2 generated without risingcontrol, FIG. 13A shows the second clock signal CLK2 generated by risingcontrol according to the first option, and FIG. 13B shows the secondclock signal CLK2 generated by rising control according to the secondoption.

Referring to FIG. 12, the generation process of the second clock signalCLK2 by the level shifter 300 may include a rising step and a fallingstep. In the rising step, the level shifter 300 may increase the voltageof the second clock signal CLK2 in two steps (the first rising stepR-STEP1, the second rising step R-STEP2) using the second gate pulsemodulation switch GPMS2 and the second rising switch S2 r based on thesecond pulse g2 of the generation clock signal GCLK. In the fallingstep, the level shifter 300 may make the voltage of the second clocksignal CLK2 fall in two steps (the first falling step F-STEP1, thesecond falling step F-STEP2) using the second gate pulse modulationswitch GPMS2 and the second falling switch S2 f based on the secondpulse m2 of the modulation clock signal MCLK.

Referring to FIG. 12, the rising of the second clock signal CLK2 may beperformed in two steps R-STEP1 and R-STEP2. The second gate pulsemodulation switch GPMS2 may be turned on before the second rising switchS2 r. Furthermore, the falling of the second clock signal CLK2 mayproceed in two steps F-STEP1 and F-STEP2. The second gate pulsemodulation switch GPMS2 may be turned on before the second fallingswitch S2 f.

The level shifter 300 may use one or more of the two options to performclock control such that the rising length CR2 of the second clock signalCLK2 is longer than the rising length CR1 of the first clock signalCLK1. The two options may include a first option for adjusting theon-resistance Ron1 of the second gate pulse modulation switch GPMS2 inthe first rising step R-STEP1, and a second option for adjusting theon-resistance of the second rising switch S1 r in the second rising stepR-STEP2.

Referring to FIG. 13A, for the first option, the on-resistance Ron2 ofthe second gate pulse modulation switch GPMS2 when the second clocksignal CLK2 rises and the on-resistance Ron2 of the second gate pulsemodulation switch GPMS2 when the second clock signal CLK2 falls may beindependently adjusted. The on-resistance Ron2 of the second gate pulsemodulation switch GPMS2 when the second clock signal CLK2 rises and theon-resistance Ron2 of the second gate pulse modulation switch GPMS2 whenthe second clock signal CLK2 falls may be the same or different fromeach other.

For example, the on-resistance Ron2 of the second gate pulse modulationswitch GPMS2 when the second clock signal CLK2 rises may be adjusted tobe greater than the on-resistance Ron2 of the second gate pulsemodulation switch GPMS2 when the second clock signal CLK2 falls.

Referring to FIG. 13A, for the first option of making the rising lengthCR2 of the second clock signal CLK2 longer than the rising length CR1 ofthe first clock signal CLK1, the on-resistance Ron2 of the second gatepulse modulation switch GPMS2 when the second clock signal CLK2 risesmay be adjusted to be greater than the on-resistance Ron1 of the firstgate pulse modulation switch GPMS1 when the first clock signal CLK1rises.

Referring to FIG. 13A, in the first rising step R-STEP1, since theon-resistance Ron2 of the second gate pulse modulation switch GPMS2involved in the rising of the second clock signal CLK2 is largelyadjusted, during the period Wg of the first rising step R-STEP1, thevoltage of the first clock signal CLK1 does not completely rise from thelow level voltage VGL to the intermediate level voltage AVDD.

Therefore, in the second rising step R-STEP2, even if the on-resistanceof the second rising switch S1 r involved in the rising of the secondclock signal CLK2 is not adjusted, since the voltage of the second clocksignal CLK2 starts to rise at a voltage lower than the intermediatelevel voltage AVDD, it takes longer for the voltage of the second clocksignal CLK2 to rise to the high level voltage VGH. Accordingly, therising length CR2 of the second clock signal CLK2 can be longer thanwhen there is no rising control as shown in FIG. 12.

Referring to FIG. 13B, in order to perform the second option by thelevel shifter 300, the on-resistance of the second rising switch S2 rmay be adjusted at the timing at which the second clock signal CLK2rises.

Referring to FIG. 13B, for the second option of making the rising lengthCR2 of the second clock signal CLK2 longer than the rising length CR1 ofthe first clock signal CLK1, the on-resistance of the second risingswitch S2 r when the second clock signal CLK2 rises may be adjusted tobe greater than the on-resistance of the first rising switch S1 r whenthe first clock signal CLK1 rises.

Referring to FIG. 13B, in the first rising step R-STEP1, theon-resistance Ron2 of the second gate pulse modulation switch GPMS2involved in the rising of the second clock signal CLK2 may not beadjusted. Accordingly, during the period Wg of the second rising stepF-STEP2, the voltage of the second clock signal CLK2 may increase fromthe low level voltage VGL to the intermediate level voltage AVDD.

However, in the second rising step (R-STEP2), since the on-resistance ofthe second rising switch S2 r involved in the rising of the second clocksignal CLK2 is largely adjusted, the voltage of the second clock signalCLK2 rises slowly. Accordingly, it may take a long time for the voltageof the second clock signal CLK2 to rise to the high level voltage VGH.Accordingly, the rising length CR2 of the second clock signal CLK2 canbecome longer than in the case where there is no rising control as shownin FIG. 12.

As described above, the display device 100 according to embodiments ofthe present disclosure controls the falling characteristic of the firstclock signal CLK1 by using a method (on-resistance adjustment method) oflargely adjusting the on-resistance of one of the first gate pulsemodulation switch GPMS1 and the first falling switch S1 f included inthe level shifter 300. Meanwhile, the display device 100 according toembodiments of the present disclosure may control the fallingcharacteristic of the first clock signal CLK1 by using another methoddifferent from the on-resistance adjustment method in the level shifter300. Hereinafter, another method for controlling the fallingcharacteristic of the first clock signal CLK1 will be described withreference to FIGS. 14A and 14B. Briefly described first, another methodof controlling the falling characteristic of the first clock signal CLK1is that the controller 140 controls the modulation clock signal MCLK sothat the level shifter 300 generates the first clock signal CLK1 whosefalling characteristic is controlled.

FIG. 14A is a driving timing diagram illustrating the first option forfalling control of the first clock signal CLK1 based on a modulationclock signal MCLK output from the controller 140 of the display device100 according to embodiments of the present disclosure. FIG. 14B is adriving timing diagram illustrating the second option for fallingcontrol of the first clock signal CLK1 based on the modulation clocksignal MCLK output from the controller 140 of the display device 100according to embodiments of the present disclosure.

Referring to FIGS. 14A and 14B, even if the on-resistance Ron1 of thefirst gate pulse modulation switch GPMS1 in the level shifter 300 or theon-resistance of the first falling switch S2 f is not adjusted, that is,even if there is no change in the level shifter 300, the fallingcharacteristic of the first clock signal CLK1 may be different from thefalling characteristic of the second clock signal CLK2.

To this end, the controller 140 performing the driving timing controlfunction may control the modulation clock signal MCLK and provide thecontrolled modulation clock signal MCLK to the level shifter 300.

Referring to FIG. 14A, the controller 140 may generate and output amodulation clock signal MCLK including a first pulse m1 having a delayedrising time. Here, the first pulse m1 of the modulation clock signalMCLK is a pulse involved in the falling of the first clock signal CLK1.In other words, as the controller 140 controls the rising timing of thefirst pulse m1 of the modulation clock signal MCLK, the fallingcharacteristic of the first clock signal CLK1 generated and output fromthe level shifter 300 can be controlled. However, although thecontroller 140 delays the rising time of the first pulse m1 of themodulation clock signal MCLK, the controller 140 may not delay thefalling time of the first pulse m1 of the modulation clock signal MCLK.

Accordingly, as shown in FIG. 14A, the pulse width Wm1 of the firstpulse m1 of the modulation clock signal MCLK may be narrower than thepulse width Wm2 of the second pulse m2 of the modulation clock signalMCLK. Here, the first pulse m1 of the modulation clock signal MCLK is apulse involved in the falling of the first clock signal CLK1, and thesecond pulse m2 of the modulation clock signal MCLK is a pulse involvedin the falling of the second clock signal CLK2.

Accordingly, the level shifter 300 may start late the first falling stepF-STEP1 with respect to the first clock signal CLK1. After the firstfalling step F-STEP1 starts late, the level shifter 300 may proceed withthe first falling step F-STEP1 during a short period corresponding tothe shortened pulse width Wm1 of the first pulse m1 of the modulationclock signal MCLK.

Accordingly, when the delayed rising time of the first pulse m1 of themodulation clock signal MCLK starts, the voltage of the first clocksignal CLK1 may start to fall from the high level voltage VGH. Inaddition, the voltage of the first clock signal CLK1 may decrease duringa short period corresponding to the shortened pulse width Wm1 of thefirst pulse m1 of the modulation clock signal MCLK.

Since the voltage of the first clock signal CLK1 falls during a shortperiod corresponding to the shortened pulse width Wm1 of the first pulsem1 of the modulation clock signal MCLK, the voltage of the first clocksignal CLK1 may not fall from the high level voltage VGH to theintermediate level voltage AVDD. Accordingly, during the first fallingstep F-STEP1, the voltage of the first clock signal CLK1 may only fallto a voltage higher than the intermediate level voltage AVDD.

Accordingly, in the second falling step F-STEP2 of the first clocksignal CLK1, the voltage of the first clock signal CLK1 may start tofall at the voltage higher than the intermediate level voltage AVDD.Accordingly, the falling completion time point at which the voltage ofthe first clock signal CLK1 falls to the low level voltage VGL may belater than the falling completion time point when there is no fallingcontrol.

As described above, the falling characteristic of the first clock signalCLK1 may be controlled by delaying the rising time of the first pulse m1of the modulation clock signal MCLK and maintaining the falling time ofthe first pulse m1 of the modulation clock signal MCLK. The fallingcompletion time of the first clock signal CLK1 according to theabove-described falling control may be later than the falling completiontime of the first clock signal CLK1 when the falling control is notperformed. According to the above-described falling control, the delayedfalling completion time of the first clock signal CLK1 may be later thanthe falling completion time of the second clock signal CLK2 to which thefalling control is not performed.

Referring to FIG. 14B, the controller 140 may generate and output themodulation clock signal MCLK including the delayed first pulse m1 byshifting both the rising timing and the falling timing equally. Thefirst pulse m1 of the modulation clock signal MCLK is a pulse involvedin the falling of the first clock signal CLK1.

Therefore, as shown in FIG. 14B, the interval d1 between the first pulseg1 of the generation clock signal GCLK and the first pulse m1 of themodulation clock signal MCLK may be longer than the interval d2 betweenthe second pulse g2 of the generation clock signal GCLK and the secondpulse m2 of the modulation clock signal MCLK. Here, the first pulse m1of the modulation clock signal MCLK is a pulse involved in the fallingof the first clock signal CLK1, and the second pulse m2 of themodulation clock signal MCLK is a pulse involved in the falling of thesecond clock signal CLK2.

Referring to FIG. 14B, the pulse width Wm1 of the first pulse m1 of themodulation clock signal MCLK may be the same as the pulse width Wm2 ofthe second pulse m2 of the modulation clock signal MCLK.

Referring to FIG. 14B, according to the shift of the first pulse m1 ofthe modulation clock signal MCLK, the level shifter 300 may start latethe first falling step F-STEP1 with respect to the first clock signalCLK1. And the level shifter 300 may proceed with the first falling stepF-STEP1 during a period corresponding to the pulse width Wm1 of thefirst pulse m1 of the modulation clock signal MCLK.

Accordingly, when the shifted rising time of the first pulse m1 of themodulation clock signal MCLK starts, the voltage of the first clocksignal CLK1 may start to fall from the high level voltage VGH. And,during a period corresponding to the pulse width Wm1 of the first pulsem1 of the modulation clock signal MCLK, the voltage of the first clocksignal CLK1 may fall from the high level voltage VGH.

At this time, since the pulse width Wm1 of the first pulse m1 of themodulation clock signal MCLK does not change, the voltage of the firstclock signal CLK1 may fall from the high level voltage VGH to theintermediate level voltage AVDD.

Thereafter, in the second falling stage F-STEP2 of the first clocksignal CLK1, the voltage of the first clock signal CLK1 may start tofall from the intermediate level voltage AVDD. Accordingly, the timeperiod during which the second falling step F-STEP2 of the first clocksignal CLK1 proceeds may not change. That is, the temporal length of thesecond falling step F-STEP2 of the first clock signal CLK1 may not bechanged. As described above, since the first pulse m1 of the modulationclock signal MCLK is entirely shifted, the falling completion time ofthe first clock signal CLK1 may not change. Here, the falling completiontime of the first clock signal CLK1 may be the time it takes for thevoltage of the first clock signal CLK1 to completely fall from the highlevel voltage VGH to the low level voltage VGL through the middle levelvoltage AVDD. The falling completion time of the first clock signal CLK1when the falling control is performed may be the same as the fallingcompletion time of the first clock signal CLK1 when there is no fallingcontrol.

However, according to the shift of the first pulse m1 of the modulationclock signal MCLK, since the falling start time of the first clocksignal CLK1 is delayed, the falling completion time of the first clocksignal CLK1 may be delayed compared to the case where there is nofalling control. Here, the delayed falling completion time of the firstclock signal CLK1 may be later than the falling completion time of thesecond clock signal CLK2.

As described above, the level shifter 300 may control the falling lengthCF1 of the first clock signal CLK1 to be long by largely adjusting theon-resistance Ron1 of the first gate pulse modulation switch GPMS1 orthe on-resistance of the first falling switch S1 f.

Hereinafter, two techniques for largely adjusting the on-resistance Ron1of the first gate pulse modulation switch GPMS1 will be described withreference to FIGS. 15A, 15B, 16A and 16B. The first technique of the twotechniques will be described with reference to FIGS. 15A and 15B, andthe second technique of the two techniques will be described withreference to FIGS. 16A and 16B. Hereinafter, the first technique may bereferred to as a switch split technique or a circuit structureutilization technique. The second technique may be referred to as a Vgscontrol technique or a gate voltage control technique.

FIG. 15A is a diagram illustrating a switch split technique foradjusting on-resistance Ron1 of the first gate pulse modulation switchGPMS1 of the level shifter 300 according to embodiments of the presentdisclosure. FIG. 15B is a diagram illustrating a switch split techniquefor adjusting on-resistance Ron2 of the second gate pulse modulationswitch GPMS2 of the level shifter 300 according to embodiments of thepresent disclosure.

Referring to FIG. 15A, the first gate pulse modulation switch GPMS1 mayinclude two or more first sub-switches GPMS1 a, GPMS1 b, and GPMS1 cconnected in parallel between the intermediate input terminal Pm and thefirst output terminal Pclk1.

Referring to FIG. 15A, two or more first sub-switches GPMS1 a, GPMS1 b,and GPMS1 c may be independently controlled on-off.

To this end, the level shifter 300 may include the clock control circuit800 and a gate driver 1500. Here, the gate driver 1500 may be includedoutside or inside the clock control circuit 800.

The gate driver 1500 may output first control signals CM1 a, CM1 b, andCM1 c for controlling the on-off of each of the two or more firstsub-switches GPMS1 a, GPMS1 b, and GPMS1 c under the control of theclock control circuit 800. The first control signals CM1 a, CM1 b, andCM1 c may be applied to a control node (gate electrode) of each of thetwo or more first sub-switches GPMS1 a, GPMS1 b, and GPMS1 c.

By adjusting the number of first sub-switches that are turned on amongtwo or more first sub-switches GPMS1 a, GPMS1 b, and GPMS1 c, theon-resistance Ron1 of the first gate pulse modulation switch GPMS1 maybe adjusted.

When the number of turned-on first sub-switches among the two or morefirst sub-switches GPMS1 a, GPMS1 b, and GPMS1 c increases, theon-resistance Ron1 of the first gate pulse modulation switch GPMS1 maydecrease. When the number of turned-on first sub-switches among the twoor more first sub-switches GPMS1 a, GPMS1 b, and GPMS1 c decreases, theon-resistance Ron1 of the first gate pulse modulation switch GPMS1 mayincrease.

That is, the on-resistance Ron1 of the first gate pulse modulationswitch GPMS1 may be inversely proportional to the number of firstsub-switches that are turned on among the two or more first sub-switchesGPMS1 a, GPMS1 b, and GPMS1 c.

Referring to FIG. 15B, the second gate pulse modulation switch GPMS2 mayinclude two or more second sub-switches GPMS2 a, GPMS2 b, and GPMS2 cconnected in parallel between the intermediate input terminal Pm and thesecond output terminal Pclk2.

Referring to FIG. 15B, two or more second sub-switches GPMS2 a, GPMS2 b,and GPMS2 c may be independently controlled on-off.

The gate driver 1500 may output second control signals CM2 a, CM2 b, andCM2 c for controlling the on-off of each of the two or more secondsub-switches GPMS2 a, GPMS2 b, and GPMS2 c under the control of theclock control circuit 800. The second control signals CM2 a, CM2 b, andCM2 c may be applied to a control node (gate electrode) of each of thetwo or more second sub-switches GPMS2 a, GPMS2 b, and GPMS2 c.

By adjusting the number of second sub-switches that are turned on amongtwo or more second sub-switches GPMS2 a, GPMS2 b, and GPMS2 c, theon-resistance Ron2 of the second gate pulse modulation switch GPMS2 maybe adjusted.

When the number of the second sub-switches that are turned on among thetwo or more second sub-switches GPMS2 a, GPMS2 b, and GPMS2 c increases,the on-resistance Ron2 of the second gate pulse modulation switch GPMS2may decrease. When the number of turned-on second sub-switches among thetwo or more second sub-switches GPMS2 a, GPMS2 b, and GPMS2 c decreases,the on-resistance Ron2 of the second gate pulse modulation switch GPMS2may increase.

That is, the on-resistance Ron2 of the second gate pulse modulationswitch GPMS2 may be inversely proportional to the number of the secondsub-switches that are turned on among the two or more secondsub-switches GPMS2 a, GPMS2 b, and GPMS2 c.

The clock control circuit 800 may adjust the number (e.g., 1) of firstsub-switches turned on at the falling of the first clock signal CLK1 tobe less than the number (e.g., 3) of second sub-switches turned on atthe falling of the second clock signal CLK2. Therefore, theon-resistance Ron1 of the first gate pulse modulation switch GPMS1 whenthe first clock signal CLK1 falls may be adjusted to be greater than theon-resistance Ron2 of the second gate pulse modulation switch GPMS2 whenthe second clock signal CLK2 falls. Accordingly, the falling length CF1of the first clock signal CLK1 may be increased.

The clock control circuit 800 may control the number (e.g., 1) of secondsub-switches turned on when the second clock signal CLK2 rises less thanthe number (e.g., 3) of first sub-switches turned on when the firstclock signal CLK1 rises. Accordingly, the on-resistance Ron2 of thesecond gate pulse modulation switch GPMS2 when the second clock signalCLK2 rise may be greater than the on-resistance Ron1 of the first gatepulse modulation switch GPMS1 when the first clock signal CLK1 rises.Accordingly, the rising length CR2 of the second clock signal CLK2 maybe increased.

As described above, the on-resistance Ron1 of the first gate pulsemodulation switch GPMS1 may be adjusted through the switch splittechnique for the first gate pulse modulation switch GPMS1. Here, theswitch split technology is a technology that controls the number ofturned-on switches.

Similar to the switch split technology for the first gate pulsemodulation switch GPMS1, the on-resistance of the first falling switchS1 f can be adjusted by applying the switch split technology for thefirst falling switch S1 f.

FIG. 16A is a diagram for explaining a Vgs control technique foradjusting an on-resistance Ron1 of the first gate pulse modulationswitch GPMS1 of the level shifter 300 according to embodiments of thepresent disclosure. FIG. 16B is a diagram for explaining a Vgs controltechnique for adjusting an on-resistance Ron2 of the second gate pulsemodulation switch GPMS2 of the level shifter 300 according toembodiments of the present disclosure.

Referring to FIG. 16A, the first gate pulse modulation switch GPMS1 maybe connected between the intermediate input terminal Pm and the firstoutput terminal Pclk1. When the first gate pulse modulation switch GPMS1is a transistor, the source electrode (or the drain electrode) of thefirst gate pulse modulation switch GPMS1 may be electrically connectedto the intermediate input terminal Pm to which the intermediate levelvoltage AVDD is input, the drain electrode (or the source electrode) ofthe first gate pulse modulation switch GPMS1 may be electricallyconnected to the first output terminal Pclk1 to which the first clocksignal CLK1 is output, and a gate electrode of the first gate pulsemodulation switch GPMS1 may be electrically connected to the gate driver1500.

Referring to FIG. 16A, the clock control circuit 800 may control a firstgate voltage corresponding to the first intermediate control signal CM1for controlling on-off of the first gate pulse modulation switch GPMS1,and may supply the first intermediate control signal CM1 correspondingto the controlled first gate voltage to the control node (gateelectrode) of the first gate pulse modulation switch GPMS1 through thegate driver 1500. Accordingly, the on-resistance Ron1 of the first gatepulse modulation switch GPMS1 may vary according to the first gatevoltage.

Referring to FIG. 16A, an on/off state of the first gate pulsemodulation switch GPMS1 may be determined according to the magnitude ofthe gate-source voltage Vgs, which is a potential difference between thegate electrode and the source electrode of the first gate pulsemodulation switch GPMS1.

When the gate-source voltage Vgs of the first gate pulse modulationswitch GPMS1 is greater than or equal to the threshold voltage Vth ofthe first gate pulse modulation switch GPMS1, the first gate pulsemodulation switch GPMS1 may be turned on.

When the gate-source voltage Vgs of the first gate pulse modulationswitch GPMS1 becomes a full turn-on voltage Vgs_on higher than thethreshold voltage Vth, the first gate pulse modulation switch GPMS1 maybe completely turned on to allow a current to flow normally. Here, thecomplete turn-on voltage Vgs_on may be a gate-source voltage in a statein which the first gate pulse modulation switch GPMS1 can flow a maximumcurrent.

Also, the turn-on degree of the first gate pulse modulation switch GPMS1may vary according to the magnitude of the gate-source voltage Vgs ofthe first gate pulse modulation switch GPMS1. That is, according to themagnitude of the gate-source voltage Vgs of the first gate pulsemodulation switch GPMS1, even when the first gate pulse modulationswitch GPMS1 is turned on, the amount of current flowing through thefirst gate pulse modulation switch GPMS1 may vary.

As such, the on-resistance Ron1 of the first gate pulse modulationswitch GPMS1 may vary according to the magnitude of the gate-sourcevoltage Vgs of the first gate pulse modulation switch GPMS1.

For example, as the gate-source voltage Vgs of the first gate pulsemodulation switch GPMS1 decreases and approaches the threshold voltageVth, the on-resistance Ron1 of the first gate pulse modulation switchGPMS1 may increase. As the gate-source voltage Vgs of the first gatepulse modulation switch GPMS1 increases and approaches the full turn-onvoltage Vgs_on, the on-resistance Ron1 of the first gate pulsemodulation switch GPMS1 may decrease.

Referring to FIG. 16B, the second gate pulse modulation switch GPMS2 maybe connected between the intermediate input terminal Pm and the secondoutput terminal Pclk2. When the second gate pulse modulation switchGPMS2 is a transistor, the source electrode or the drain electrode ofthe second gate pulse modulation switch GPMS2 may be electricallyconnected to the intermediate input terminal Pm to which theintermediate level voltage AVDD is input, the drain electrode or thesource electrode of the second gate pulse modulation switch GPMS2 may beelectrically connected to the second output terminal Pclk2 to which thesecond clock signal CLK2 is output, and a gate electrode of the secondgate pulse modulation switch GPMS2 may be electrically connected to thegate driver 1500.

Referring to FIG. 16B, the clock control circuit 800 may control thesecond gate voltage corresponding to the second intermediate controlsignal CM2 for controlling the on-off of the second gate pulsemodulation switch GPMS2, and may supply the second intermediate controlsignal CM2 corresponding to the controlled second gate voltage to thecontrol node (gate electrode) of the second gate pulse modulation switchGPMS2 through the gate driver 1500. Accordingly, the on-resistance Ron2of the second gate pulse modulation switch GPMS2 may vary according tothe second gate voltage.

Referring to FIG. 16B, on/off of the second gate pulse modulation switchGPMS2 may be determined according to the magnitude of the gate-sourcevoltage Vgs, which is a potential difference between the gate electrodeand the source electrode of the second gate pulse modulation switchGPMS2.

When the gate-source voltage Vgs of the second gate pulse modulationswitch GPMS2 is greater than or equal to the threshold voltage Vth ofthe second gate pulse modulation switch GPMS2, the second gate pulsemodulation switch GPMS2 may be turned on.

When the gate-source voltage Vgs of the second gate pulse modulationswitch GPMS2 becomes a full turn-on voltage Vgs_on having a highthreshold voltage Vth, the second gate pulse modulation switch GPMS2 maybe completely turned on to allow a current to flow normally Here, thecomplete turn-on voltage Vgs_on may be a gate-source voltage in a statein which the second gate pulse modulation switch GPMS2 can flow amaximum current.

Also, the turn-on degree of the second gate pulse modulation switchGPMS2 may vary according to the magnitude of the gate-source voltage Vgsof the second gate pulse modulation switch GPMS2. That is, according tothe magnitude of the gate-source voltage Vgs of the second gate pulsemodulation switch GPMS2, even when the second gate pulse modulationswitch GPMS2 is turned on, the amount of current flowing through thesecond gate pulse modulation switch GPMS2 may vary.

As described above, the on-resistance Ron2 of the second gate pulsemodulation switch GPMS2 may vary according to the magnitude of thegate-source voltage Vgs of the second gate pulse modulation switchGPMS2.

For example, as the gate-source voltage Vgs of the second gate pulsemodulation switch GPMS2 decreases and approaches the threshold voltageVth, the on-resistance Ron2 of the second gate pulse modulation switchGPMS2 may increase. As the gate-source voltage Vgs of the second gatepulse modulation switch GPMS2 increases and approaches the full turn-onvoltage Vgs_on, the on-resistance Ron2 of the second gate pulsemodulation switch GPMS2 may decrease.

The clock control circuit 800 may lower Vgs of the first gate pulsemodulation switch GPMS1 when the first clock signal CLK1 falls than Vgsof the second gate pulse modulation switch GPMS2 when the second clocksignal CLK2 falls. Accordingly, the on-resistance Ron1 of the first gatepulse modulation switch GPMS1 when the first clock signal CLK1 falls maybe adjusted to be greater than the on-resistance Ron2 of the second gatepulse modulation switch GPMS2 when the second clock signal CLK2 falls.Accordingly, the falling length CF1 of the first clock signal CLK1 maybe increased.

The clock control circuit 800 may lower Vgs of the second gate pulsemodulation switch GPMS2 when the second clock signal CLK2 rises than Vgsof the first gate pulse modulation switch GPMS1 when the first clocksignal CLK1 rises. Accordingly, the on-resistance Ron2 of the secondgate pulse modulation switch GPMS2 when the second clock signal CLK2rises may be adjusted to be greater than the on-resistance Ron1 of thefirst gate pulse modulation switch GPMS1 when the first clock signalCLK1 rises. Accordingly, the rising length CR2 of the second clocksignal CLK2 may be increased.

As described above, the on-resistance Ron1 of the first gate pulsemodulation switch GPMS1 may be adjusted through the Vgs controltechnique for the first gate pulse modulation switch GPMS1.

In the same way as the Vgs control technique for the first gate pulsemodulation switch GPMS1, the on-resistance of the first falling switchS1 f may be adjusted by applying the Vgs control technique for the firstfalling switch S1 f.

In the above, when the gate driving circuit 130 has a structure in whichtwo gate output buffer circuits GBUF1 and GBUF2 share one Q node, asshown in FIG. 5, a method for compensating for gate output deviation andthe level shifter 300 have been described.

Below, when the gate driving circuit 130 has a structure in which fourgate output buffer circuits GBUF1 to GBUF4 share one Q node, a method ofcompensating for a gate output deviation and a level shifter 300 will bebriefly described. In the above description, overlapping parts areomitted, and the content that differs is briefly explained.

FIG. 17 illustrates a gate signal output system of the display device100 according to embodiments of the present disclosure. FIG. 18 is agate driving circuit 300 having a structure in which four gate outputbuffer circuits GBUF1 to GBUF4 share one Q node in the display device100 according to embodiments of the present disclosure.

Referring to FIG. 17, the level shifter 300 may output four clocksignals CLK1 to CLK4. The gate driving circuit 130 may output the fourgate signals Vgout1 to Vgout4 to the four gate lines GL1 to GL4 based onthe four clock signals CLK1 to CLK4.

Referring to FIG. 18, the gate driving circuit 130 may include first tofourth gate output buffer circuits GBUF1 to GBUF4 and a control circuit400 for controlling the first to fourth gate output buffer circuitsGBUF1 to GBUF4.

The first gate output buffer circuit GBUF1 may output the first gatesignal Vgout1 to the first gate line GL1 through the first gate outputterminal Ng1 based on the first clock signal CLK1 input to the firstclock input terminal Nc1.

The first gate output buffer circuit GBUF1 may include a first pull-uptransistor Tu1 electrically connected between the first clock inputterminal Nc1 and the first gate output terminal Ng1 and controlled bythe voltage of the Q node, and a first pull-down transistor Td1electrically connected between the first gate output terminal Ng1 andthe ground input terminal Ns to which the ground voltage VSS1 is input,and controlled by the voltage of the QB node.

The second gate output buffer circuit GBUF2 may output the second gatesignal Vgout2 to the second gate line GL2 through the second gate outputterminal Ng2 based on the second clock signal CLK2 input to the secondclock input terminal Nc2.

The second gate output buffer circuit GBUF2 may include a second pull-uptransistor Tu2 electrically connected between the second clock inputterminal Nc2 and the second gate output terminal Ng2 and controlled bythe voltage of the Q node, and a second pull-down transistor Td2electrically connected between the second gate output terminal Ng2 andthe ground input terminal Ns and controlled by the voltage of the QBnode.

The third gate output buffer circuit GBUF3 may output the third gatesignal Vgout3 to the third gate line GL3 through the third gate outputterminal Ng3 based on the third clock signal CLK3 input to the thirdclock input terminal Nc3.

The third gate output buffer circuit GBUF3 may include a third pull-uptransistor Tu3 electrically connected between the third clock inputterminal Nc3 and the third gate output terminal Ng3 and controlled bythe voltage of the Q node, and a third pull-down transistor Td3electrically connected between the third gate output terminal Ng3 andthe ground input terminal Ns and controlled by the voltage of the QBnode.

The fourth gate output buffer circuit GBUF4 may output the fourth gatesignal Vgout4 to the fourth gate line GL4 through the fourth gate outputterminal Ng4 based on the fourth clock signal CLK4 input to the fourthclock input terminal Nc4.

The fourth gate output buffer circuit GBUF4 may include a fourth pull-uptransistor Tu4 electrically connected between the fourth clock inputterminal Nc4 and the fourth gate output terminal Ng4 and controlled bythe voltage of the Q node, and a fourth pull-down transistor Td4electrically connected between the fourth gate output terminal Ng4 andthe ground input terminal Ns and controlled by the voltage of the QBnode.

For example, when the gate driving circuit 130 performs gate driving ineight phases, the level shifter 300 may generate and output eight clocksignals CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, and CLK8. And the gatedriving circuit 130 may perform gate driving using eight clock signalsCLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, and CLK8.

As in the above example, when the gate driving circuit 130 performs gatedriving in 8 phases and has a structure in which four gate output buffercircuits GBUF1 to GBUF4 share one Q node, as shown in FIG. 18, the eightclock signals CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, and CLK8 may begrouped into first to fourth groups. The first and fifth clock signalsCLK1 and CLK5 included in the first group may have the same signalcharacteristics. The first and fifth clock signals CLK1 and CLK5included in the first group may be input to the first gate output buffercircuits GBUF1 connected to different Q nodes to be used to generate thefirst and fifth gate signals. The second and sixth clock signals CLK2and CLK6 included in the second group may have the same signalcharacteristics. The second and sixth clock signals CLK2 and CLK6included in the second group may be input to the second gate outputbuffer circuits GBUF2 connected to different Q nodes and used togenerate the second and sixth gate signals. The third and seventh clocksignals CLK3 and CLK7 included in the third group may have the samesignal characteristics. The third and seventh clock signals CLK3 andCLK7 included in the third group may be input to the third gate outputbuffer circuits GBUF3 connected to different Q nodes and used togenerate the third and seventh gate signals. The fourth and eighth clocksignals CLK4 and CLK8 included in the fourth group may have the samesignal characteristics. The fourth and eighth clock signals CLK4 andCLK8 included in the fourth group may be input to the fourth gate outputbuffer circuits GBUF4 connected to different Q nodes and used togenerate the fourth and eighth gate signals. Accordingly, below, thefirst to fourth clock signals CLK1 to CLK4 are described asrepresentative clock signals of the first to fourth groups,respectively.

FIG. 19 is a diagram illustrating a characteristic deviation betweengate signals output from the gate driving circuit 130 of FIG. 18according to one embodiment. FIG. 20 is a diagram for explaining acharacteristic deviation compensation function between gate signalsoutput from the gate driving circuit 130 of FIG. 18 according to oneembodiment.

Referring to FIG. 19, the level shifter 300 may output first to fourthclock signals CLK1 to CLK4 having the same signal waveform and signalcharacteristics. The gate driving circuit 130 may output first to fourthgate signals Vgout1 to Vgout4 by using the first to fourth clock signalsCLK1 to CLK4 input from the level shifter 300.

As described above, when the gate driving circuit 130 performs overlapgate driving and has a Q node sharing structure without performing aclock signal control function to compensate for characteristic deviationbetween gate signals, characteristic deviation between gate signals mayoccur.

Not performing the clock signal control function to compensate for thecharacteristic deviation between the gate signals may mean that thefirst to fourth clock signals CLK1 to CLK4 have the same signalwaveform. The fact that the first to fourth clock signals CLK1 to CLK4have the same signal waveform means that the rising characteristics(rising length) and falling characteristics (falling length) of thefirst to fourth clock signals CLK1 to CLK4 are the same.

Referring to FIG. 19, among the first to fourth gate signals Vgout1 toVgout4, the turn-on voltage level section of the first gate signalVgout1 proceeds at the earliest timing, and the turn-on voltage levelsection of the fourth gate signal Vgout4 may proceed at the slowesttiming. In this case, the rising length R1 of the turn-on voltage levelsection of the first gate signal Vgout1 among the first to fourth gatesignals Vgout1 to Vgout4 may be the longest. That is, the risingcharacteristic of the first gate signal Vgout1 among the first to fourthgate signals Vgout1 to Vgout4 may be the worst.

The falling length R4 in the turn-on voltage level section of the fourthgate signal Vgout4 among the first to fourth gate signals Vgout1 toVgout4 may be the longest. That is, the falling characteristic of thefourth gate signal Vgout4 among the first to fourth gate signals Vgout1to Vgout4 may be the worst.

Comparing the rising characteristics (rising length) of each of thefirst to fourth gate signals Vgout1 to Vgout4, the rising characteristicof the first gate signal Vgout1 may be the worst, and the risingcharacteristic of the fourth gate signal Vgout4 may be the best. Therising characteristic of the second gate signal Vgout2 may be the secondworst, and a rising characteristic of the third gate signal Vgout3 maybe third worst. That is, the rising length R1 of the first gate signalVgout1 may be the longest, and the rising length R4 of the fourth gatesignal Vgout4 may be the shortest. The rising length R2 of the secondgate signal Vgout2 may be the second longest, and the rising length R3of the third gate signal Vgout3 may be the third longest (R1>R2>R3>R4).

However, it does not change that the rising length R1 of the first gatesignal Vgout1 is the longest among the first to fourth gate signalsVgout1 to Vgout4, and the magnitude relationship of the rising lengthsR2, R3, and R4 between the second to fourth gate signals Vgout2 toVgout4 may be variously changed.

When comparing the falling characteristics (falling length) of each ofthe first to fourth gate signals (Vgout1 to Vgout4), the fallingcharacteristic of the fourth gate signal Vgout4 may be the worst, andthe falling characteristic of the first gate signal Vgout1 may be thebest. The falling characteristic of the third gate signal Vgout3 may bethe second worst, and the falling characteristic of the second gatesignal Vgout2 may be the third worst. That is, the falling length F4 ofthe fourth gate signal Vgout4 may be the longest, and the falling lengthF1 of the first gate signal Vgout1 may be the shortest. The fallinglength F3 of the third gate signal Vgout3 may be the second longest, andthe falling length F2 of the second gate signal Vgout2 may be the thirdlongest (F1<F2<F3<F4).

However, it does not change that the falling length F4 of the fourthgate signal Vgout4 is the longest among the first to fourth gate signalsVgout1 to Vgout4, and the magnitude relationship of the falling lengthsF1, F2, and F3 between the first to third gate signals Vgout1 to Vgout3may vary.

In order to reduce the characteristic deviation between the first tofourth gate signals Vgout1 to Vgout4, that is, to compensate for thecharacteristic deviation between the gate signals, the level shifter 300may perform a clock signal control function. Here, the characteristicdeviation may include a rising characteristic deviation and a fallingcharacteristic deviation.

Referring to FIG. 20, in order to reduce a characteristic deviationbetween the first to fourth gate signals Vgout1 to Vgout4, the levelshifter 300 may control signal characteristics of one or more of thefirst to fourth clock signals CLK1 to CLK4. Here, the signalcharacteristic may include at least one of a rising characteristic and afalling characteristic. For example, the level shifter 300 may controlthe respective falling lengths CF1, CF2, and CF3 of the first to thirdclock signals CLK1 to CLK3 to become longer. Accordingly, the fallinglengths F1, F2, and F3 of each of the first, second and third gatesignals Vgout1, Vgout2, and Vgout3 may be similar to the falling lengthF4 of the fourth gate signal Vgout4 having the worst fallingcharacteristics.

Referring to FIG. 20, a turn-on level voltage section of the first gatesignal Vgout1 and a turn-on level voltage section of the second gatesignal Vgout2 may overlap. The turn-on level voltage section of thesecond gate signal Vgout2 and a turn-on level voltage section of thethird gate signal Vgout3 may overlap. And the turn-on level voltagesection of the third gate signal Vgout3 and a turn-on level voltagesection of the fourth gate signal Vgout4 may overlap.

Referring to FIG. 20, the first gate signal Vgout1 may have a turn-onlevel voltage section at a faster timing than the last fourth gatesignal Vgout4 among the first to fourth gate signals Vgout1 to Vgout4.In this case, the falling length CF1 of the first clock signal CLK1 maybe longer than the falling length CF4 of the fourth clock signal CLK4,or the rising length CR4 of the fourth clock signal CLK4 may be longerthan the rising length CR1 of the first clock signal CLK1. It will beexplained again below.

Referring to FIG. 20, as long as the falling length CF4 of the fourthclock signal CLK4 is the shortest, the magnitude relation of therespective falling lengths CF1 to CF3 of the first to third clocksignals CLK1 to CLK3 may be changed.

Referring to FIG. 20, for example, the falling length CF4 of the fourthclock signal CLK4 is the shortest, the falling length CF3 of the thirdclock signal CLK3 is the second shortest, the falling length CF2 of thesecond clock signal CLK2 is the third shortest, and the falling lengthCF1 of the first clock signal CLK1 may be the longest (CF4<CF3<CF2<CF1).

Referring to FIG. 20, in order to reduce the characteristic deviation(rising characteristic deviation, falling characteristic deviation)between the first to fourth gate signals Vgout1 to Vgout4, the levelshifter 300 may control the rising lengths CR2 to CR4 of each of thesecond to fourth clock signals CLK2 to CLK4 to be longer. Accordingly,the rising lengths R2 to R4 of each of the second to fourth gate signalsVgout2 to Vgout4 may be similar to the rising length R1 of the firstgate signal Vgout1 having the worst rising characteristic.

Referring to FIG. 20, as long as the rising length CR1 of the firstclock signal CLK1 is the shortest, the magnitude relation of the risinglengths CR2 to CR4 of the second to fourth clock signals CLK2 to CLK4may be changed.

Referring to FIG. 20, for example, the rising length CR1 of the firstclock signal CLK1 may be the shortest, the rising length CR2 of thesecond clock signal CLK2 is the second shortest, the rising length CR3of the third clock signal CLK3 is the third shortest, and the risinglength CR4 of the fourth clock signal CLK4 may be the longest(CR1<CR2<CR3<CR4).

FIG. 21 is the level shifter 300 according to embodiments of the presentdisclosure.

The level shifter 300 according to embodiments of the present disclosureillustrated in FIG. 21 is for a gate driving circuit 130 having a Q nodesharing structure in which four gate output buffers GBUF1 to GBUF4 shareone Q node.

The structure of the level shifter 300 of FIG. 21 is an extension of thestructure of the level shifter 300 of FIG. 8, and may have the samestructural concept as the structure of the level shifter 300 of FIG. 8.The operation of the level shifter 300 of FIG. 21 is an extension of theoperation of the level shifter 300 of FIG. 8, and may have the sameconcept as the operation of the level shifter 300 of FIG. 8. Here, thelevel shifter 300 of FIG. 21 is for the gate driving circuit 130 has a Qnode sharing structure in which four gate output buffers GBUF1 to GBUF4share one Q node. The level shifter 300 of FIG. 8 is for gate drivingcircuit 130 having a Q node sharing structure in which two gate outputbuffers GBUF1 and GBUF2 share one Q node.

Since the level shifter 300 of FIG. 21 generates and outputs four clocksignals CLK1 to CLK4, the number of output terminals and the number ofclock output circuits is different, and the remaining structure is thesame as that of the level shifter 300 of FIG. 8.

Referring to FIG. 21, the level shifter 300 according to embodiments ofthe present disclosure may include: input terminals Ph, Pl, Pm, Pgclk,and Pmclk; output terminals Pclk1, Pclk2, Pclk3, and Pclk4; first tofourth clock output circuits COC1 to COC4 configured to output the firstto fourth clock signals CLK1 to CLK4, respectively; and a clock controlcircuit 800 configured to control the first to fourth clock outputcircuits COC1 to COC4.

Referring to FIG. 21, the first clock output circuit COC1 may include: afirst rising switch S1 r for controlling the electrical connectionbetween the high input terminal Ph and the first output terminal Pclk1;a first falling switch S1 f for controlling the electrical connectionbetween the low input terminal Pl and the first output terminal Pclk1;and a first gate pulse modulation switch GPMS1 for controlling anelectrical connection between the intermediate input terminal Pm and thefirst output terminal Pclk1.

Referring to FIG. 21, the second clock output circuit COC2 may include:a second rising switch S2 r for controlling an electrical connectionbetween the high input terminal Ph and the second output terminal Pclk2;a second falling switch S2 f controlling the electrical connectionbetween the low input terminal Pl and the second output terminal Pclk2;and a second gate pulse modulation switch GPMS2 for controlling theelectrical connection between the intermediate input terminal Pm and thesecond output terminal Pclk2.

Referring to FIG. 21, the third clock output circuit COC3 may includethe third rising switch S3 r for controlling an electrical connectionbetween the high input terminal Ph and the third output terminal Pclk3,the third falling switch S3 f controlling the electrical connectionbetween the low input terminal Pl and the third output terminal Pclk3,and the third gate pulse modulation switch GPMS3 for controlling theelectrical connection between the intermediate input terminal Pm and thethird output terminal Pclk3.

Referring to FIG. 21, the fourth clock output circuit COC4 may include afourth rising switch S4 r for controlling the electrical connectionbetween the high input terminal Ph and the fourth output terminal Pclk4,a fourth falling switch S4 f that controls the electrical connectionbetween the low input terminal Pl and the fourth output terminal Pclk4,and a fourth gate pulse modulation switch GPMS4 for controlling theelectrical connection between the intermediate input terminal Pm and thefourth output terminal Pclk4.

Referring to FIG. 21, the clock control circuit 800 may output a firstrising control signal C1 r for controlling the switching operation ofthe first rising switch S1 r, a first falling control signal C1 f forcontrolling the switching operation of the first falling switch S1 f,and a first intermediate control signal CM1 for controlling a switchingoperation of the first gate pulse modulation switch GPMS1. The clockcontrol circuit 800 may output a second rising control signal C2 r forcontrolling the switching operation of the second rising switch S2 r, asecond falling control signal C2 f for controlling the switchingoperation of the second falling switch S2 f, and a second intermediatecontrol signal CM2 for controlling a switching operation of the secondgate pulse modulation switch GPMS2.

Referring to FIG. 21, the clock control circuit 800 may output a thirdrising control signal C3 r for controlling the switching operation ofthe third rising switch S3 r, a third falling control signal C3 f forcontrolling the switching operation of the third falling switch S3 f,and a third intermediate control signal CM3 for controlling theswitching operation of the third gate pulse modulation switch GPMS3. Theclock control circuit 800 may output a fourth rising control signal C4 rfor controlling the switching operation of the fourth rising switch S4r, a fourth falling control signal C4 f for controlling the switchingoperation of the fourth falling switch S4 f, and a fourth intermediatecontrol signal CM4 for controlling the switching operation of the fourthgate pulse modulation switch GPMS4.

Meanwhile, each of the first to fourth gate pulse modulation switchesGPMS1 to GPMS3, the first to fourth rising switches S1 r to S4 r, andthe first to fourth falling switches S1 f to S4 f may have anon-resistance. Here, the on-resistance of the switch is a resistancethat prevents the flow of current flowing through the switch when acontrol signal (gate voltage) capable of turning on the switch isapplied to the switch.

The on-resistances Ron1 to Ron4 of the first to fourth gate pulsemodulation switches GPMS1 to GPMS4 may be greater than theon-resistances of the first to fourth rising switches S1 r to S4 r. Theon-resistances Ron1 to Ron4 of the first to fourth gate pulse modulationswitches GPMS1 to GPMS4 may be greater than the on-resistances of thefirst to fourth falling switches S1 f to S4 f.

Each of the on-resistances Ron1 to Ron4 of the first to fourth gatepulse modulation switches GPMS1 to GPMS4 included in the level shifter300 according to embodiments of the present disclosure may beindependently adjusted. Each of the on-resistances Ron1 to Ron4 of thefirst to fourth gate pulse modulation switches GPMS1 to GPMS4 includedin the level shifter 300 according to embodiments of the presentdisclosure may be independently adjusted during the rising period and/orthe falling period of the first to fourth clock signals CLK1 to CLK4.

In addition, in the level shifter 300 according to embodiments of thepresent disclosure, the on-resistance of the first to fourth risingswitches S1 r to S4 r can be independently adjusted, or theon-resistance of the first to fourth falling switches S1 f to S4 f canbe independently adjusted.

The level shifter 300 according to embodiments of the present disclosuremay further include the first gate pulse modulation switch GPMS1associated with the generation of the first clock signal CLK1, thesecond gate pulse modulation switch GPMS2 associated with the generationof the second clock signal CLK2, the third gate pulse modulation switchGPMS3 associated with the generation of the third clock signal CLK3, andthe fourth gate pulse modulation switch GPMS4 associated with thegeneration of the fourth clock signal CLK4. In this respect, the levelshifter 300 according to embodiments of the present disclosure has aunique feature.

FIG. 22 is a graph for explaining an effect of the characteristicdeviation compensation function between gate signals Vgout1 and Vgout2under the Q node sharing structure as shown in FIG. 5 in the displaydevice 100 according to embodiments of the present disclosure.

FIG. 22 is a graph showing the first gate signal Vgout1, the second gatesignal Vgout2, and the Q node voltage before and after applying thecharacteristic deviation compensation control between the gate signalsVgout1 and Vgout2 under the Q node sharing structure as shown in FIG. 5.

Referring to FIG. 22, before applying the characteristic deviationcompensation control between the gate signals, the fallingcharacteristics of the first and second gate signals Vgout1 and Vgout2are as follows. However, the falling length is the difference betweenthe time when the voltage level becomes 90% of the voltage level beforefalling and the time when the voltage level becomes 10% of the voltagelevel before falling.

Referring to FIG. 22, before applying the characteristic deviationcompensation control between the gate signals, the falling length of thefirst gate signal Vgout1 is 1.64 μs, and the falling length of thesecond gate signal Vgout2 is 2.08 μs.

Referring to FIG. 22, before applying the characteristic deviationcompensation control between the gate signals, the falling lengthdifference (falling deviation) between the first gate signal Vgout1 andthe second gate signal Vgout2 is 0.44 μs (=2.08 μs−1.64 μs).

In the effect verification simulation, only the falling control thatlengthens the falling length CF1 of the first clock signal CLK1 wasapplied when the characteristic deviation compensation control betweenthe gate signals was applied.

Referring to FIG. 22, the falling characteristic of the first gatesignal Vgout1 after applying the characteristic deviation compensationcontrol between the gate signals is as follows. In the falling processof the first gate signal Vgout1, the difference between the time whenthe voltage level becomes 90% of the voltage level before falling andthe time when the voltage level becomes 10% of the voltage level beforefalling is measured as the falling length. The measured falling lengthis 1.94 μs. This is longer than 1.64 μs, which is the falling lengthbefore applying the characteristic deviation compensation controlbetween gate signals.

Referring to FIG. 22, the falling characteristic of the second gatesignal Vgout2 after applying the characteristic deviation compensationcontrol between the gate signals does not change as follows. In thefalling process of the second gate signal Vgout2, the difference betweenthe time when the voltage level becomes 90% of the voltage level beforefalling and the time when the voltage level becomes 10% of the voltagelevel before falling is measured as the falling length do. The measuredfalling length is 2.08 μs.

Referring to FIG. 22, after applying the characteristic deviationcompensation control between the gate signals, the falling lengthdifference (falling deviation) between the first gate signal Vgout1 andthe second gate signal Vgout2 is 0.14 μs (=2.08 μs−1.94 μs). This is asignificantly reduced value than 0.44 μs, which is the falling lengthdifference before applying the characteristic deviation compensationcontrol between gate signals.

Therefore, through the falling control of the first clock signal CLK1,it is possible to reduce the deviation of the falling characteristicsbetween the first gate signal Vgout1 and the second gate signal Vgout2.

FIG. 23 is a diagram for explaining an effect of a characteristicdeviation compensation function between gate signals Vgout1, Vgout2,Vgout3, and Vgout4 under the Q node sharing structure as shown in FIG.18 in the display device 100 according to embodiments of the presentdisclosure.

FIG. 23 is a graph illustrating first to fourth gate signals Vgout1 toVgout4 and Q node voltages before and after applying the characteristicdeviation compensation control between the first to fourth gate signalsVgout1 to Vgout4 under the Q node sharing structure as shown in FIG. 18.

Referring to FIG. 23, before applying the characteristic deviationcompensation control between the gate signals, the fallingcharacteristics of the first to fourth gate signals Vgout1 to Vgout4 areas follows. However, the falling length is the difference between thetime when the voltage level becomes 90% of the voltage level beforefalling and the time when the voltage level becomes 10% of the voltagelevel before falling.

Referring to FIG. 23, before applying the characteristic deviationcompensation control between the gate signals, the falling length of thefirst gate signal Vgout1 is 1.91 μs. The falling length of the secondgate signal Vgout2 is 1.83 μs. The falling length of the third gatesignal Vgout3 is 2.17 μs. Furthermore, the falling length of the fourthgate signal Vgout4 is 2.42 μs.

Referring to FIG. 23, before applying the characteristic deviationcompensation control between the gate signals, the maximum fallinglength difference (maximum falling deviation) between the first tofourth gate signals Vgout1 to Vgout4 is 0.59 μs (=2.42 μs−1.83 μs).

In the effect verification simulation, for the compensation control ofthe characteristic deviation between the gate signals, the fallingcontrol was applied. Accordingly, the falling length CF1 of the firstclock signal CLK1 is the longest, the falling length CF2 of the secondclock signal CLK2 becomes the second longest, and the falling length CF3of the third clock signal CLK3 becomes the third longest.

Referring to FIG. 23, after applying the characteristic deviationcompensation control between the gate signals, the fallingcharacteristics of the first to fourth gate signals Vgout1 to Vgout4 areas follows.

Referring to FIG. 23, after applying the characteristic deviationcompensation control between the gate signals, the falling length of thefirst gate signal Vgout1 is 2.061 μs, the falling length of the secondgate signal Vgout2 is 1.96 μs, the falling length of the third gatesignal Vgout3 is 1.99 μs, and the falling length of the fourth gatesignal Vgout4 is 2.36 μs.

Referring to FIG. 23, after applying the characteristic deviationcompensation control between the gate signals, the maximum fallinglength difference (maximum falling deviation) between the first tofourth gate signals Vgout1 to Vgout4 is 0.40 μs (=2.36 μs−1.96 μs). Thisis a significantly reduced value than 0.59 μs, which is the fallinglength difference before applying the characteristic deviationcompensation control between gate signals.

Accordingly, through the falling control of the first to fourth clocksignals CLK1 to CLK4, it is possible to reduce the deviation in thefalling characteristics between the first to fourth gate signals Vgout1to Vgout4.

According to embodiments of the present disclosure, it is possible toprovide the level shifter 300 and the display device 100 that can reducea characteristic variation between gate signals and thereby improveimage quality.

According to embodiments of the present disclosure, it is possible toprovide the level shifter 300 and the display device 100 capable ofvariously controlling a rising characteristic and/or a fallingcharacteristic of clock signals.

According to embodiments of the present disclosure, it is possible toprovide the level shifter 300 and the display device 100 capable ofreducing the size of an arrangement area of the gate driving circuit 130and reducing characteristic variation between gate signals even if thegate driving circuit is disposed on the display panel 110 in a panelbuilt-in type.

The above description has been presented to enable any person skilled inthe art to make and use the technical idea of the present invention, andhas been provided in the context of a particular application and itsrequirements. Various modifications, additions and substitutions to thedescribed embodiments will be readily apparent to those skilled in theart, and the general principles defined herein may be applied to otherembodiments and applications without departing from the spirit and scopeof the present invention. The above description and the accompanyingdrawings provide an example of the technical idea of the presentinvention for illustrative purposes only. That is, the disclosedembodiments are intended to illustrate the scope of the technical ideaof the present invention. Thus, the scope of the present invention isnot limited to the embodiments shown, but is to be accorded the widestscope consistent with the claims. The scope of protection of the presentinvention should be construed based on the following claims, and alltechnical ideas within the scope of equivalents thereof should beconstrued as being included within the scope of the present invention.

What is claimed is:
 1. A level shifter comprising: a first outputterminal outputting a first clock signal; a second output terminaloutputting a second clock signal having a different rising length or adifferent falling length than a rising length or a falling length of thefirst clock signal, respectively; a high input terminal to which a highlevel voltage is input; a low input terminal to which a low levelvoltage is input, the low level voltage less than the high levelvoltage; an intermediate input terminal to which an intermediate levelvoltage is input, the intermediate level voltage less than the highlevel voltage and greater than the low level voltage; a first clockoutput circuit including a first rising switch configured to control anelectrical connection between the high input terminal and the firstoutput terminal, a first falling switch configured to control anelectrical connection between the low input terminal and the firstoutput terminal, and a first gate pulse modulation switch configured tocontrol an electrical connection between the intermediate input terminaland the first output terminal; and a second clock output circuitincluding a second rising switch configured to control an electricalconnection between the high input terminal and the second outputterminal, a second falling switch configured to control an electricalconnection between the low input terminal and the second outputterminal, and a second gate pulse modulation switch configured tocontrol an electrical connection between the intermediate input terminaland the second output terminal.
 2. The level shifter of claim 1, whereinan on-resistance of the first gate pulse modulation switch is greaterthan an on-resistance of the first rising switch and an on-resistance ofthe first falling switch, and wherein an on-resistance of the secondgate pulse modulation switch is greater than an on-resistance of thesecond rising switch and an on-resistance of the second falling switch.3. The level shifter of claim 1, wherein a falling length of the firstclock signal is longer than a falling length of the second clock signal.4. The level shifter of claim 1, wherein an on-resistance of the firstgate pulse modulation switch when the first clock signal falls from afirst level to a second level that is less than the first level isgreater than an on-resistance of the second gate pulse modulation switchwhen the second clock signal falls from the first level to the secondlevel.
 5. The level shifter of claim 1, wherein an on-resistance of thefirst falling switch when the first clock signal falls is greater thanan on-resistance of the second falling switch when the second clocksignal falls.
 6. The level shifter of claim 1, wherein a rising lengthof the second clock signal is longer than a rising length of the firstclock signal.
 7. The level shifter of claim 1, wherein an on-resistanceof the second gate pulse modulation switch when the second clock signalrises is greater than an on-resistance of the first gate pulsemodulation switch when the first clock signal rises.
 8. The levelshifter of claim 1, wherein an on-resistance of the second rising switchwhen the second clock signal rises is greater than an on-resistance ofthe first rising switch when the first clock signal rises.
 9. The levelshifter of claim 1, wherein an on-resistance of the first gate pulsemodulation switch when the first clock signal falls is greater than theon-resistance of the first gate pulse modulation switch when the firstclock signal rises.
 10. The level shifter of claim 1, wherein anon-resistance of the second gate pulse modulation switch when the secondclock signal rises is greater than the on-resistance of the second gatepulse modulation switch when the second clock signal falls.
 11. Thelevel shifter of claim 1, further comprising a clock control circuitconfigured to control the first clock output circuit and the secondclock output circuit based on a generation clock signal and a modulationclock signal, wherein the clock control circuit is configured to outputcontrol signals for controlling an on state or an off state of each ofthe first rising switch, the first falling switch, and the first gatepulse modulation switch based on a first pulse of the generation clocksignal and a first pulse of the modulation clock signal, and wherein theclock control circuit is configured to output control signals forcontrolling an on state or an off state of each of the second risingswitch, the second falling switch, and the second gate pulse modulationswitch based on a second pulse of the generation clock signal and asecond pulse of the modulation clock signal.
 12. The level shifter ofclaim 1, wherein the first gate pulse modulation switch includes two ormore first sub-switches connected in parallel between the intermediateinput terminal and the first output terminal, and an on state or offstate of the two or more first sub-switches are independentlycontrolled, wherein an on-resistance of the first gate pulse modulationswitch is in inverse proportion to a number of turned-on firstsub-switches among the two or more first sub-switches, wherein thesecond gate pulse modulation switch includes two or more secondsub-switches connected in parallel between the intermediate inputterminal and the second output terminal, and wherein an on-resistance ofthe second gate pulse modulation switch is in inverse proportion to anumber of turned-on second sub-switches among the two or more secondsub-switches.
 13. The level shifter of claim 1, further comprising aclock control circuit configured to control a first gate voltage and asecond gate voltage, wherein the first gate voltage is a control signalfor controlling an on state or an off state of the first gate pulsemodulation switch, and the second gate voltage is a control signal forcontrolling an on state or an off state of the second gate pulsemodulation switch, and wherein an on-resistance of the first gate pulsemodulation switch is changed according to the first gate voltage, and anon-resistance of the second gate pulse modulation switch is changedaccording to the second gate voltage.
 14. The level shifter of claim 1,wherein a rising of the first clock signal includes a first risingperiod in which the voltage of the first clock signal is changed fromthe low level voltage to the intermediate level voltage by the firstgate pulse modulation switch and a second rising period subsequent tothe first rising period in which the voltage of the first clock signalis changed from the intermediate level voltage to the high level voltageby the first rising switch, and wherein a falling of the first clocksignal includes a first falling period in which the voltage of the firstclock signal is changed from the high level voltage to the intermediatelevel voltage or a voltage greater than the intermediate level voltageby the first gate pulse modulation switch and a second falling periodsubsequent to the first falling period in which the voltage of the firstclock signal is changed from the intermediate level voltage or thevoltage greater than the intermediate level voltage to the low levelvoltage by the first falling switch.
 15. The level shifter of claim 1,wherein a rising of the second clock signal includes a first risingperiod in which the voltage of the second clock signal is changed fromthe low level voltage to the intermediate level voltage or a voltageless than the intermediate level voltage by the second gate pulsemodulation switch and a second rising period subsequent to the firstrising period in which the voltage of the second clock signal is changedfrom the intermediate level voltage or the voltage less than theintermediate level voltage to the high level voltage by the secondrising switch, and wherein the falling of the second clock signalincludes a first falling period in which the voltage of the second clocksignal is changed from the high level voltage to the intermediate levelvoltage by the second gate pulse modulation switch and a second fallingperiod subsequent to the first falling period in which the voltage ofthe second clock signal is changed from the intermediate level voltageto the low level voltage by the second falling switch.
 16. The levelshifter of claim 1, further comprising: a third output terminaloutputting a third clock signal having a different rising length or adifferent falling length than the first and second clock signals; afourth output terminal outputting a fourth clock signal having adifferent rising length or a different falling length than the first,second and third clock signals; a third clock output circuit including athird rising switch for controlling an electrical connection between thehigh input terminal and the third output terminal, a third fallingswitch for controlling an electrical connection between the low inputterminal and the third output terminal, and a third gate pulsemodulation switch for controlling an electrical connection between theintermediate input terminal and the third output terminal; and a fourthclock output circuit including a fourth rising switch for controlling anelectrical connection between the high input terminal and the fourthoutput terminal, a fourth falling switch controlling an electricalconnection between the low input terminal and the fourth outputterminal, and a fourth gate pulse modulation switch for controlling anelectrical connection between the intermediate input terminal and thefourth output terminal.
 17. A display device comprising: a substrate; aplurality of gate lines disposed on the substrate; and a gate drivingcircuit disposed on or connected to the substrate and configured tooutput a first gate signal and a second gate signal to a first gate lineand a second gate line among the plurality of gate lines based on afirst clock signal and a second clock signal, wherein the gate drivingcircuit comprises: a first gate output buffer circuit configured tooutput the first gate signal based on the first clock signal; a secondgate output buffer circuit configured to output the second gate signalbased on the second clock signal; and a gate output control circuitconfigured to control the first gate output buffer circuit and thesecond gate output buffer circuit, wherein the first gate output buffercircuit comprises: a first pull-up transistor connected between a firstclock input terminal to which the first clock signal is input and afirst gate output terminal to which the first gate signal is output; anda first pull-down transistor connected between the first gate outputterminal and a base input terminal to which a base voltage is input,wherein the second gate output buffer circuit comprises: a secondpull-up transistor connected between a second clock input terminal towhich the second clock signal is input and a second gate output terminalto which the second gate signal is output; and a second pull-downtransistor connected between the second gate output terminal and a baseinput terminal to which a base voltage is input, wherein a gate node ofthe first pull-up transistor and a gate node of the second pull-uptransistor are electrically connected, wherein a gate node of the firstpull-down transistor and a gate node of the second pull-down transistorare electrically connected, and wherein a falling length of the firstclock signal is different from a falling length of the second clocksignal, or a rising length of the second clock signal is different froma rising length of the first clock signal.
 18. The display device ofclaim 17, wherein the falling length of the first clock signal is longerthan the falling length of the second clock signal.
 19. The displaydevice of claim 18, wherein a difference between a falling length of thefirst gate signal and a falling length of the second gate signal is lessthan a difference between the falling length of the first clock signaland the falling length of the second clock signal.
 20. The displaydevice of claim 18, further comprising a level shifter configured tooutput the first clock signal and the second clock signal, wherein thelevel shifter comprises: a first output terminal outputting a firstclock signal; a second output terminal outputting a second clock signalhaving a different rising length or a different falling length than thefirst clock signal; a high input terminal to which a high level voltageis input; a low input terminal to which a low level voltage is input,the low level voltage less than the high level voltage; an intermediateinput terminal to which an intermediate level voltage is input, theintermediate level voltage less than the high level voltage and greaterthan the low level voltage; a first clock output circuit including afirst rising switch configured to control an electrical connectionbetween the high input terminal and the first output terminal, a firstfalling switch configured to control an electrical connection betweenthe low input terminal and the first output terminal, and a first gatepulse modulation switch configured to control an electrical connectionbetween the intermediate input terminal and the first output terminal;and a second clock output circuit including a second rising switchconfigured to control an electrical connection between the high inputterminal and the second output terminal, a second falling switchconfigured to control an electrical connection between the low inputterminal and the second output terminal, and a second gate pulsemodulation switch configured to control an electrical connection betweenthe intermediate input terminal and the second output terminal.